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Searched refs:opcode (Results 1 – 25 of 72) sorted by relevance

123

/art/disassembler/
Ddisassembler_x86.cc202 std::ostringstream opcode; in DumpInstruction() local
219 case rm8_r8: opcode << #opname; store = true; has_modrm = true; byte_operand = true; break; \ in DumpInstruction()
220 case rm32_r32: opcode << #opname; store = true; has_modrm = true; break; \ in DumpInstruction()
221 case r8_rm8: opcode << #opname; load = true; has_modrm = true; byte_operand = true; break; \ in DumpInstruction()
222 case r32_rm32: opcode << #opname; load = true; has_modrm = true; break; \ in DumpInstruction()
223 case ax8_i8: opcode << #opname; ax = true; immediate_bytes = 1; byte_operand = true; break; \ in DumpInstruction()
224 case ax32_i32: opcode << #opname; ax = true; immediate_bytes = 4; break; in DumpInstruction()
261 opcode << "push"; in DumpInstruction()
266 opcode << "pop"; in DumpInstruction()
272 opcode << "movsxd"; in DumpInstruction()
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Ddisassembler_arm.cc248 std::string opcode; in DumpArm() local
256 opcode = "bkpt"; in DumpArm()
263 opcode = (((instruction >> 5) & 1) ? "blx" : "bx"); in DumpArm()
270 opcode = kDataProcessingOperations[op]; in DumpArm()
309 opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : "")); in DumpArm()
339 opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a')); in DumpArm()
346 opcode = (bl ? "bl" : "b"); in DumpArm()
353 opcode = "???"; in DumpArm()
356 opcode += kConditionCodeNames[cond]; in DumpArm()
357 opcode += suffixes; in DumpArm()
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Ddisassembler_mips.cc179 std::string opcode; in Dump() local
185 opcode = StringPrintf("op=%d fn=%d", op, function); in Dump()
189 opcode = gMipsInstructions[i].name; in Dump()
210 case 0: opcode += ".s"; break; in Dump()
211 case 1: opcode += ".d"; break; in Dump()
212 case 4: opcode += ".w"; break; in Dump()
213 case 5: opcode += ".l"; break; in Dump()
214 case 6: opcode += ".ps"; break; in Dump()
215 default: opcode += ".?"; break; in Dump()
259 << StringPrintf(": %08x\t%-7s ", instruction, opcode.c_str()) in Dump()
/art/compiler/dex/quick/
Dmir_to_lir-inl.h44 inline LIR* Mir2Lir::RawLIR(DexOffset dalvik_offset, int opcode, int op0, in RawLIR() argument
48 insn->opcode = opcode; in RawLIR()
56 if ((opcode == kPseudoTargetLabel) || (opcode == kPseudoSafepointPC) || in RawLIR()
57 (opcode == kPseudoExportedPC)) { in RawLIR()
69 inline LIR* Mir2Lir::NewLIR0(int opcode) { in NewLIR0() argument
70 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & NO_OPERAND)) in NewLIR0()
71 << GetTargetInstName(opcode) << " " << opcode << " " in NewLIR0()
74 LIR* insn = RawLIR(current_dalvik_offset_, opcode); in NewLIR0()
79 inline LIR* Mir2Lir::NewLIR1(int opcode, int dest) { in NewLIR1() argument
80 DCHECK(IsPseudoLirOp(opcode) || (GetTargetInstFlags(opcode) & IS_UNARY_OP)) in NewLIR1()
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Ddex_file_method_inliner.cc111 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); in GetInvokeReg()
112 if (Instruction::FormatOf(invoke->dalvikInsn.opcode) == Instruction::k3rc) { in GetInvokeReg()
115 DCHECK_EQ(Instruction::FormatOf(invoke->dalvikInsn.opcode), Instruction::k35c); in GetInvokeReg()
122 DCHECK(!MIR::DecodedInstruction::IsPseudoMirOp(invoke->dalvikInsn.opcode)); in WideArgIsInConsecutiveDalvikRegs()
123 return Instruction::FormatOf(invoke->dalvikInsn.opcode) == Instruction::k3rc || in WideArgIsInConsecutiveDalvikRegs()
433 if (kIntrinsicIsStatic[intrinsic.opcode] != (info->type == kStatic)) { in GenIntrinsic()
437 switch (intrinsic.opcode) { in GenIntrinsic()
505 LOG(FATAL) << "Unexpected intrinsic opcode: " << intrinsic.opcode; in GenIntrinsic()
543 switch (method.opcode) { in GenInline()
563 LOG(FATAL) << "Unexpected inline op: " << method.opcode; in GenInline()
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Dmir_to_lir.cc325 switch (special.opcode) { in GenSpecialCase()
328 DCHECK_EQ(mir->dalvikInsn.opcode, Instruction::RETURN_VOID); in GenSpecialCase()
366 if (special.opcode != kInlineOpReturnArg) { in GenSpecialCase()
393 Instruction::Code opcode = mir->dalvikInsn.opcode; in CompileDalvikInstruction() local
403 uint64_t attrs = MIRGraph::GetDataFlowAttributes(opcode); in CompileDalvikInstruction()
437 switch (opcode) { in CompileDalvikInstruction()
615 GenCmpFP(opcode, rl_dest, rl_src[0], rl_src[1]); in CompileDalvikInstruction()
632 bool is_taken = EvaluateBranch(opcode, mir_graph_->ConstantValue(rl_src[0].orig_sreg), in CompileDalvikInstruction()
646 GenCompareAndBranch(opcode, rl_src[0], rl_src[1], taken, fall_through); in CompileDalvikInstruction()
661 bool is_taken = EvaluateBranch(opcode, mir_graph_->ConstantValue(rl_src[0].orig_sreg), 0); in CompileDalvikInstruction()
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Dlocal_optimizations.cc156 if (this_lir->flags.is_nop || IsPseudoLirOp(this_lir->opcode)) { in ApplyLoadStoreElimination()
160 uint64_t target_flags = GetTargetInstFlags(this_lir->opcode); in ApplyLoadStoreElimination()
210 if (check_lir->flags.is_nop || IsPseudoLirOp(check_lir->opcode)) { in ApplyLoadStoreElimination()
221 uint64_t check_flags = GetTargetInstFlags(check_lir->opcode); in ApplyLoadStoreElimination()
333 if (IsPseudoLirOp(this_lir->opcode)) { in ApplyLoadHoisting()
337 uint64_t target_flags = GetTargetInstFlags(this_lir->opcode); in ApplyLoadHoisting()
412 if (stop_here || !IsPseudoLirOp(check_lir->opcode)) { in ApplyLoadHoisting()
443 if (!IsPseudoLirOp(dep_lir->opcode) && in ApplyLoadHoisting()
444 (GetTargetInstFlags(dep_lir->opcode) & IS_LOAD)) { in ApplyLoadHoisting()
461 if (GetTargetInstFlags(cur_lir->opcode) & IS_LOAD) { in ApplyLoadHoisting()
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/art/compiler/dex/quick/x86/
Dutility_x86.cc30 int opcode; in OpFpRegCopy() local
35 opcode = kX86MovsdRR; in OpFpRegCopy()
39 opcode = kX86MovssRR; in OpFpRegCopy()
41 opcode = kX86MovdxrRR; in OpFpRegCopy()
45 opcode = kX86MovdrxRR; in OpFpRegCopy()
48 DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL); in OpFpRegCopy()
49 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_dest.GetReg(), r_src.GetReg()); in OpFpRegCopy()
121 X86OpCode opcode = kX86Bkpt; in OpReg() local
123 case kOpNeg: opcode = r_dest_src.Is64Bit() ? kX86Neg64R : kX86Neg32R; break; in OpReg()
124 case kOpNot: opcode = r_dest_src.Is64Bit() ? kX86Not64R : kX86Not32R; break; in OpReg()
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Dx86_lir.h407 #define BinaryOpCode(opcode) \ argument
408 opcode ## 8MR, opcode ## 8AR, opcode ## 8TR, \
409 opcode ## 8RR, opcode ## 8RM, opcode ## 8RA, opcode ## 8RT, \
410 opcode ## 8RI, opcode ## 8MI, opcode ## 8AI, opcode ## 8TI, \
411 opcode ## 16MR, opcode ## 16AR, opcode ## 16TR, \
412 opcode ## 16RR, opcode ## 16RM, opcode ## 16RA, opcode ## 16RT, \
413 opcode ## 16RI, opcode ## 16MI, opcode ## 16AI, opcode ## 16TI, \
414 opcode ## 16RI8, opcode ## 16MI8, opcode ## 16AI8, opcode ## 16TI8, \
415 opcode ## 32MR, opcode ## 32AR, opcode ## 32TR, \
416 opcode ## 32RR, opcode ## 32RM, opcode ## 32RA, opcode ## 32RT, \
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/art/compiler/dex/quick/mips/
Dutility_mips.cc26 int opcode; in OpFpRegCopy() local
30 opcode = kMipsFmovd; in OpFpRegCopy()
34 opcode = kMipsFmovs; in OpFpRegCopy()
40 opcode = kMipsMtc1; in OpFpRegCopy()
44 opcode = kMipsMfc1; in OpFpRegCopy()
47 LIR* res = RawLIR(current_dalvik_offset_, opcode, r_src.GetReg(), r_dest.GetReg()); in OpFpRegCopy()
117 MipsOpCode opcode = kMipsNop; in OpReg() local
120 opcode = kMipsJalr; in OpReg()
128 return NewLIR2(opcode, rRA, r_dest_src.GetReg()); in OpReg()
136 MipsOpCode opcode = kMipsNop; in OpRegImm() local
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Dassemble_mips.cc41 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \ argument
44 {k3, k3s, k3e}}, opcode, flags, name, fmt, size}
463 int opcode = lir->opcode; in ConvertShortToLongBranch() local
465 switch (opcode) { in ConvertShortToLongBranch()
471 case kMipsBeq: opcode = kMipsBne; break; in ConvertShortToLongBranch()
472 case kMipsBne: opcode = kMipsBeq; break; in ConvertShortToLongBranch()
473 case kMipsBeqz: opcode = kMipsBnez; break; in ConvertShortToLongBranch()
474 case kMipsBgez: opcode = kMipsBltz; break; in ConvertShortToLongBranch()
475 case kMipsBgtz: opcode = kMipsBlez; break; in ConvertShortToLongBranch()
476 case kMipsBlez: opcode = kMipsBgtz; break; in ConvertShortToLongBranch()
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Dfp_mips.cc24 void MipsMir2Lir::GenArithOpFloat(Instruction::Code opcode, in GenArithOpFloat() argument
33 switch (opcode) { in GenArithOpFloat()
61 LOG(FATAL) << "Unexpected opcode: " << opcode; in GenArithOpFloat()
70 void MipsMir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble() argument
75 switch (opcode) { in GenArithOpDouble()
103 LOG(FATAL) << "Unpexpected opcode: " << opcode; in GenArithOpDouble()
116 void MipsMir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, in GenConversion() argument
120 switch (opcode) { in GenConversion()
152 LOG(FATAL) << "Unexpected opcode: " << opcode; in GenConversion()
168 void MipsMir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, in GenCmpFP() argument
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Dcodegen_mips.h75 const char* GetTargetInstFmt(int opcode);
76 const char* GetTargetInstName(int opcode);
79 uint64_t GetTargetInstFlags(int opcode);
87 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
93 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
95 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
97 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
99 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
101 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
109 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
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/art/compiler/dex/quick/arm/
Dutility_arm.cc224 ArmOpcode opcode = kThumbBkpt; in OpReg() local
227 opcode = kThumbBlxR; in OpReg()
230 opcode = kThumbBx; in OpReg()
235 return NewLIR1(opcode, r_dest_src.GetReg()); in OpReg()
242 ArmOpcode opcode = kThumbBkpt; in OpRegRegShift() local
245 opcode = (thumb_form) ? kThumbAdcRR : kThumb2AdcRRR; in OpRegRegShift()
248 opcode = (thumb_form) ? kThumbAndRR : kThumb2AndRRR; in OpRegRegShift()
251 opcode = (thumb_form) ? kThumbBicRR : kThumb2BicRRR; in OpRegRegShift()
255 opcode = (thumb_form) ? kThumbCmnRR : kThumb2CmnRR; in OpRegRegShift()
259 opcode = kThumbCmpRR; in OpRegRegShift()
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Dtarget_arm.cc167 int opcode = lir->opcode; in SetupTargetResourceMasks() local
226 if (opcode == kThumbPush || opcode == kThumbPop) { in SetupTargetResourceMasks()
228 if ((opcode == kThumbPush) && (use_mask->Intersects(r8Mask))) { in SetupTargetResourceMasks()
231 } else if ((opcode == kThumbPop) && (def_mask->Intersects(r8Mask))) { in SetupTargetResourceMasks()
297 static char* DecodeRegList(int opcode, int vector, char* buf, size_t buf_size) { in DecodeRegList() argument
304 if (opcode == kThumbPush && i == 8) { in DecodeRegList()
306 } else if (opcode == kThumbPop && i == 8) { in DecodeRegList()
470 DecodeRegList(lir->opcode, operand, tbuf, arraysize(tbuf)); in BuildInsnString()
538 return ((lir->opcode == kThumbBUncond) || (lir->opcode == kThumb2BUncond)); in IsUnconditionalBranch()
556 if (ArmMir2Lir::EncodingMap[i].opcode != i) { in ArmMir2Lir()
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Dassemble_arm.cc39 #define ENCODING_MAP(opcode, skeleton, k0, ds, de, k1, s1s, s1e, k2, s2s, s2e, \ argument
42 {k3, k3s, k3e}}, opcode, flags, name, fmt, size, fixup}
1073 int opcode = lir->opcode; in EncodeLIRs() local
1074 if (IsPseudoLirOp(opcode)) { in EncodeLIRs()
1075 if (UNLIKELY(opcode == kPseudoPseudoAlign4)) { in EncodeLIRs()
1084 const ArmEncodingMap *encoder = &EncodingMap[lir->opcode]; in EncodeLIRs()
1273 if (kIsDebugBuild && (((lir->opcode == kThumbAddPcRel) && (delta > 1020)) || in AssembleLIR()
1274 ((lir->opcode == kThumbLdrPcRel) && (delta > 1020)))) { in AssembleLIR()
1279 if (((lir->opcode == kThumb2LdrPcRel12) && (delta > 4091)) || in AssembleLIR()
1280 ((lir->opcode == kThumb2LdrdPcRel8) && (delta > 1020)) || in AssembleLIR()
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/art/runtime/
Ddex_instruction.cc62 #define INSTRUCTION_SIZE(opcode, c, p, format, r, i, a, v) \ argument
63 ((opcode == NOP) ? -1 : \
92 Code opcode = static_cast<Code>(insn & 0xFF); in CanFlowThrough() local
93 return FlagsOf(opcode) & Instruction::kContinue; in CanFlowThrough()
138 const char* opcode = kInstructionNames[Opcode()]; in DumpString() local
140 case k10x: os << opcode; break; in DumpString()
141 case k12x: os << StringPrintf("%s v%d, v%d", opcode, VRegA_12x(), VRegB_12x()); break; in DumpString()
142 case k11n: os << StringPrintf("%s v%d, #%+d", opcode, VRegA_11n(), VRegB_11n()); break; in DumpString()
143 case k11x: os << StringPrintf("%s v%d", opcode, VRegA_11x()); break; in DumpString()
144 case k10t: os << StringPrintf("%s %+d", opcode, VRegA_10t()); break; in DumpString()
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/art/compiler/dex/quick/arm64/
Dutility_arm64.cc91 bool opcode_is_wide = IS_WIDE(lir->opcode); in GetLoadStoreSize()
92 ArmOpcode opcode = UNWIDE(lir->opcode); in GetLoadStoreSize() local
93 DCHECK(!IsPseudoLirOp(opcode)); in GetLoadStoreSize()
94 const ArmEncodingMap *encoder = &EncodingMap[opcode]; in GetLoadStoreSize()
101 uint64_t check_flags = GetTargetInstFlags(lir->opcode); in GetInstructionOffset()
334 bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value, Instruction::Code opcode) { in InexpensiveConstantInt() argument
335 switch (opcode) { in InexpensiveConstantInt()
418 ArmOpcode opcode = LIKELY(low_bits == 0) ? kA64Mov2rr : kA64Mvn2rr; in LoadConstantNoClobber() local
419 res = NewLIR2(opcode, r_dest.GetReg(), rwzr); in LoadConstantNoClobber()
469 ArmOpcode opcode = LIKELY(value == 0) ? WIDE(kA64Mov2rr) : WIDE(kA64Mvn2rr); in LoadConstantWide() local
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/art/runtime/quick/
Dinline_method_analyser.h133 InlineMethodOpcode opcode; member
155 static constexpr bool IsInstructionIGet(Instruction::Code opcode) { in IsInstructionIGet() argument
156 return Instruction::IGET <= opcode && opcode <= Instruction::IGET_SHORT; in IsInstructionIGet()
159 static constexpr bool IsInstructionIPut(Instruction::Code opcode) { in IsInstructionIPut() argument
160 return Instruction::IPUT <= opcode && opcode <= Instruction::IPUT_SHORT; in IsInstructionIPut()
163 static constexpr uint16_t IGetVariant(Instruction::Code opcode) { in IGetVariant() argument
164 return opcode - Instruction::IGET; in IGetVariant()
167 static constexpr uint16_t IPutVariant(Instruction::Code opcode) { in IPutVariant() argument
168 return opcode - Instruction::IPUT; in IPutVariant()
Dinline_method_analyser.cc97 Instruction::Code opcode = instruction->Opcode(); in AnalyseMethodCode() local
99 switch (opcode) { in AnalyseMethodCode()
102 method->opcode = kInlineOpNop; in AnalyseMethodCode()
155 result->opcode = kInlineOpReturnArg; in AnalyseReturnMethod()
192 result->opcode = kInlineOpNonWideConst; in AnalyseConstMethod()
203 Instruction::Code opcode = instruction->Opcode(); in AnalyseIGetMethod() local
204 DCHECK(IsInstructionIGet(opcode)); in AnalyseIGetMethod()
208 if (!(return_opcode == Instruction::RETURN_WIDE && opcode == Instruction::IGET_WIDE) && in AnalyseIGetMethod()
209 !(return_opcode == Instruction::RETURN_OBJECT && opcode == Instruction::IGET_OBJECT) && in AnalyseIGetMethod()
210 !(return_opcode == Instruction::RETURN && opcode != Instruction::IGET_WIDE && in AnalyseIGetMethod()
[all …]
/art/compiler/dex/
Dlocal_value_numbering_test.cc44 Instruction::Code opcode; member
53 #define DEF_CONST(opcode, reg, value) \ argument
54 { opcode, value, 0u, 0, { }, 1, { reg } }
55 #define DEF_CONST_WIDE(opcode, reg, value) \ argument
56 { opcode, value, 0u, 0, { }, 2, { reg, reg + 1 } }
57 #define DEF_CONST_STRING(opcode, reg, index) \ argument
58 { opcode, index, 0u, 0, { }, 1, { reg } }
59 #define DEF_IGET(opcode, reg, obj, field_info) \ argument
60 { opcode, 0u, field_info, 1, { obj }, 1, { reg } }
61 #define DEF_IGET_WIDE(opcode, reg, obj, field_info) \ argument
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Dmir_optimization.cc64 switch (d_insn->opcode) { in DoConstantPropagation()
135 if ((mir->dalvikInsn.opcode == Instruction::MOVE_RESULT) || in FindMoveResult()
136 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_OBJECT) || in FindMoveResult()
137 (mir->dalvikInsn.opcode == Instruction::MOVE_RESULT_WIDE)) { in FindMoveResult()
141 if (MIR::DecodedInstruction::IsPseudoMirOp(mir->dalvikInsn.opcode)) { in FindMoveResult()
175 if (static_cast<int>(mir->dalvikInsn.opcode) == kMirOpPhi) { in FindPhi()
187 switch (mir->dalvikInsn.opcode) { in SelectKind()
215 static constexpr bool IsInstructionIfCcZ(Instruction::Code opcode) { in IsInstructionIfCcZ() argument
216 return Instruction::IF_EQZ <= opcode && opcode <= Instruction::IF_LEZ; in IsInstructionIfCcZ()
219 static constexpr ConditionCode ConditionCodeForIfCcZ(Instruction::Code opcode) { in ConditionCodeForIfCcZ() argument
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Dmir_graph.h261 static uint32_t GetStartUseIndex(Instruction::Code opcode);
280 Instruction::Code opcode; member
282 explicit DecodedInstruction():vA(0), vB(0), vB_wide(0), vC(0), opcode(Instruction::NOP) { in DecodedInstruction()
291 static bool IsPseudoMirOp(Instruction::Code opcode) { in IsPseudoMirOp()
292 return static_cast<int>(opcode) >= static_cast<int>(kMirOpFirst); in IsPseudoMirOp()
295 static bool IsPseudoMirOp(int opcode) { in IsPseudoMirOp()
296 return opcode >= static_cast<int>(kMirOpFirst); in IsPseudoMirOp()
300 …return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kInvoke) == Instruc… in IsInvoke()
304 …return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kStore) == Instruct… in IsStore()
308 …return !IsPseudoMirOp(opcode) && ((Instruction::FlagsOf(opcode) & Instruction::kLoad) == Instructi… in IsLoad()
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Dmir_graph.cc142 decoded_instruction->opcode = inst->Opcode(); in ParseInsn()
233 DCHECK(static_cast<int>(insn->dalvikInsn.opcode) == kMirOpCheck || in SplitBlock()
234 !MIR::DecodedInstruction::IsPseudoMirOp(insn->dalvikInsn.opcode)); in SplitBlock()
242 int opcode = p->dalvikInsn.opcode; in SplitBlock() local
249 if ((opcode == kMirOpCheck) || !MIR::DecodedInstruction::IsPseudoMirOp(opcode)) { in SplitBlock()
403 switch (insn->dalvikInsn.opcode) { in ProcessCanBranch()
428 LOG(FATAL) << "Unexpected opcode(" << insn->dalvikInsn.opcode << ") with kBranch set"; in ProcessCanBranch()
485 if (insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH) { in ProcessCanSwitch()
515 (insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH) ? kPackedSwitch : kSparseSwitch; in ProcessCanSwitch()
527 (insn->dalvikInsn.opcode == Instruction::PACKED_SWITCH) ? in ProcessCanSwitch()
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/art/runtime/arch/x86/
Dfault_handler_x86.cc101 uint8_t opcode = *pc++; in GetInstructionSize() local
111 switch (opcode) { in GetInstructionSize()
130 opcode = *pc++; in GetInstructionSize()
139 if (x86_64 && opcode >= 0x40 && opcode <= 0x4f) { in GetInstructionSize()
140 opcode = *pc++; in GetInstructionSize()
143 if (opcode == 0x0f) { in GetInstructionSize()
146 opcode = *pc++; in GetInstructionSize()
152 switch (opcode) { in GetInstructionSize()
167 switch (opcode) { in GetInstructionSize()
201 VLOG(signals) << "Unhandled x86 instruction with opcode " << static_cast<int>(opcode); in GetInstructionSize()

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