| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 210 int32_t true_val, int32_t false_val, RegStorage rs_dest, in GenSelectConst32() argument
212 DCHECK(!left_op.IsPair() && !right_op.IsPair() && !rs_dest.IsPair()); in GenSelectConst32()
213 DCHECK(!left_op.IsFloat() && !right_op.IsFloat() && !rs_dest.IsFloat()); in GenSelectConst32()
218 LoadConstantNoClobber(rs_dest, true_val); in GenSelectConst32()
222 const bool dest_intersect = IsSameReg(rs_dest, left_op) || IsSameReg(rs_dest, right_op); in GenSelectConst32()
225 if (zero_one_case && IsByteRegister(rs_dest)) { in GenSelectConst32()
227 LoadConstantNoClobber(rs_dest, 0); in GenSelectConst32()
231 NewLIR2(kX86Set8R, rs_dest.GetReg(), in GenSelectConst32()
234 NewLIR2(rs_dest.Is64Bit() ? kX86Movzx8qRR : kX86Movzx8RR, rs_dest.GetReg(), rs_dest.GetReg()); in GenSelectConst32()
246 LoadConstantNoClobber(rs_dest, false_val); in GenSelectConst32()
[all …]
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| D | target_x86.cc | 1790 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); in GenConst128() local
1792 int reg = rs_dest.GetReg(); in GenConst128()
1831 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); in GenMoveVector() local
1833 NewLIR2(kX86Mova128RR, rs_dest.GetReg(), rs_src.GetReg()); in GenMoveVector()
2278 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); in GenSetVector() local
2337 NewLIR2(op_mov, rs_dest.GetReg(), rl_src.reg.GetReg()); in GenSetVector()
2340 NewLIR3(op_low, rs_dest.GetReg(), rs_dest.GetReg(), imm); in GenSetVector()
2344 NewLIR3(op_high, rs_dest.GetReg(), rs_dest.GetReg(), imm); in GenSetVector()
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| D | codegen_x86.h | 241 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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| /art/compiler/dex/quick/arm64/ |
| D | int_arm64.cc | 92 RegStorage rs_dest, int result_reg_class) { in GenSelect() argument
107 bool is_wide = rs_dest.Is64Bit(); in GenSelect()
114 left_op = rs_dest; in GenSelect()
115 LoadConstantNoClobber(rs_dest, true_val); in GenSelect()
134 right_op = rs_dest; in GenSelect()
135 LoadConstantNoClobber(rs_dest, false_val); in GenSelect()
171 NewLIR4(is_wide ? WIDE(opcode) : opcode, rs_dest.GetReg(), left_op.GetReg(), right_op.GetReg(), in GenSelect()
176 int32_t true_val, int32_t false_val, RegStorage rs_dest, in GenSelectConst32() argument
178 DCHECK(rs_dest.Valid()); in GenSelectConst32()
180 GenSelect(true_val, false_val, code, rs_dest, dest_reg_class); in GenSelectConst32()
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| D | codegen_arm64.h | 189 int32_t true_val, int32_t false_val, RegStorage rs_dest,
387 void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest,
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| /art/compiler/dex/quick/mips/ |
| D | int_mips.cc | 219 int32_t true_val, int32_t false_val, RegStorage rs_dest, in GenSelectConst32() argument
223 LoadConstant(rs_dest, false_val); // Favors false. in GenSelectConst32()
225 LoadConstant(rs_dest, true_val); in GenSelectConst32()
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| D | codegen_mips.h | 123 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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| /art/compiler/dex/quick/arm/ |
| D | int_arm.cc | 207 int32_t true_val, int32_t false_val, RegStorage rs_dest, in GenSelectConst32() argument
215 OpRegRegReg(kOpSub, rs_dest, left_op, right_op); in GenSelectConst32()
218 LoadConstant(rs_dest, code == kCondEq ? false_val : true_val); in GenSelectConst32()
225 LoadConstant(rs_dest, true_val); // .eq case - load true in GenSelectConst32()
226 LoadConstant(rs_dest, false_val); // .eq case - load true in GenSelectConst32()
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| D | codegen_arm.h | 124 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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| /art/compiler/dex/quick/ |
| D | mir_to_lir.h | 1345 int32_t true_val, int32_t false_val, RegStorage rs_dest,
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