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Searched refs:s_reg_low (Results 1 – 19 of 19) sorted by relevance

/art/compiler/dex/quick/
Dgen_loadstore.cc45 int pmap_index = SRegToPMap(rl_dest.s_reg_low); in Workaround7250540()
49 int base_vreg = mir_graph_->SRegToVReg(rl_dest.s_reg_low); in Workaround7250540()
51 if (mir_graph_->SRegToVReg(mir_graph_->reg_location_[i].s_reg_low) == base_vreg) { in Workaround7250540()
69 … StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), temp_reg, k32, kNotVolatile); in Workaround7250540()
96 LoadRefDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, kNotVolatile); in LoadValueDirect()
98 Load32Disp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest); in LoadValueDirect()
129 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, k64, kNotVolatile); in LoadValueDirectWide()
161 DCHECK_NE(rl_src.s_reg_low, INVALID_SREG); in LoadValue()
181 (rl_dest.s_reg_low != live_sreg_)); in StoreValue()
182 live_sreg_ = rl_dest.s_reg_low; in StoreValue()
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Dralloc_util.cc714 NullifyRange(rl.reg, rl.s_reg_low); in ResetDefLoc()
724 NullifyRange(rs, rl.s_reg_low); in ResetDefLocWide()
826 int s_reg = loc.s_reg_low; in MarkLive()
1014 RegStorage reg = AllocLiveReg(loc.s_reg_low, loc.ref ? kRefReg : kAnyReg, false); in UpdateLoc()
1039 RegStorage reg = AllocLiveReg(loc.s_reg_low, kAnyReg, true); in UpdateLocWide()
1097 DCHECK_NE(loc.s_reg_low, INVALID_SREG); in EvalLocWide()
1098 DCHECK_NE(GetSRegHi(loc.s_reg_low), INVALID_SREG); in EvalLocWide()
1137 DCHECK_NE(loc.s_reg_low, INVALID_SREG); in EvalLoc()
1155 int p_map_idx = SRegToPMap(loc.s_reg_low); in CountRefs()
1247 core_regs[dalvik_regs + ct_idx].s_reg = ct->s_reg_low; in DoPromotion()
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Dcodegen_util.cc63 rl_src.s_reg_low--; in IsInexpensiveConstant()
1207 …return (abs(mir_graph_->SRegToVReg(rl_src.s_reg_low) - mir_graph_->SRegToVReg(rl_dest.s_reg_low)) … in BadOverlap()
1299 if (info->IsLive() && (info->SReg() == loc.s_reg_low)) { in NarrowRegLoc()
1301 info_new->MarkLive(loc.s_reg_low); in NarrowRegLoc()
Dgen_invoke.cc808 Load32Disp(TargetPtrReg(kSp), SRegOffset(rl_arg.s_reg_low) + 4, reg); in GenDalvikArgsNoRange()
926 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); in GenDalvikArgsRange()
933 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); in GenDalvikArgsRange()
946 int start_offset = SRegOffset(info->args[3].s_reg_low); in GenDalvikArgsRange()
Dgen_common.cc434 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); in GenFilledNewArray()
464 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); in GenFilledNewArray()
/art/compiler/dex/quick/x86/
Dfp_x86.cc127 int src_v_reg_offset = SRegOffset(rl_src.s_reg_low); in GenLongToFP()
128 int dest_v_reg_offset = SRegOffset(rl_dest.s_reg_low); in GenLongToFP()
218 ClobberSReg(rl_dest.s_reg_low); in GenConversion()
239 ClobberSReg(rl_dest.s_reg_low); in GenConversion()
277 ClobberSReg(rl_dest.s_reg_low); in GenConversion()
302 ClobberSReg(rl_dest.s_reg_low); in GenConversion()
344 int src1_v_reg_offset = SRegOffset(rl_src1.s_reg_low); in GenRemFP()
345 int src2_v_reg_offset = SRegOffset(rl_src2.s_reg_low); in GenRemFP()
346 int dest_v_reg_offset = SRegOffset(rl_dest.s_reg_low); in GenRemFP()
460 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
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Dcall_x86.cc86 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); in GenLargePackedSwitch()
160 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); in GenFillArrayData()
292 int displacement = SRegOffset(base_of_code_->s_reg_low); in GenEntrySequence()
Dint_x86.cc988 LoadWordDisp(rs_rX86_SP, SRegOffset(rl_src_obj.s_reg_low) + push_offset, rs_obj); in GenInlinedCas()
995 LoadWordDisp(rs_rX86_SP, SRegOffset(rl_src_offset.s_reg_low) + push_offset, rs_off); in GenInlinedCas()
1077 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); in OpPcRelLoad()
1408 int displacement = SRegOffset(rl_src1.s_reg_low); in GenMulLongConst()
1416 GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); in GenMulLongConst()
1417 GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); in GenMulLongConst()
1485 bool is_square = mir_graph_->SRegToVReg(rl_src1.s_reg_low) == in GenMulLong()
1486 mir_graph_->SRegToVReg(rl_src2.s_reg_low); in GenMulLong()
1501 LoadBaseDisp(rs_rX86_SP, SRegOffset(rl_src1.s_reg_low) + HIWORD_OFFSET, rs_r1, k32, in GenMulLong()
1511 int displacement = SRegOffset(rl_src2.s_reg_low); in GenMulLong()
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Dtarget_x86.cc917 int displacement = SRegOffset(rl_dest.s_reg_low); in GenConstWide()
946 << ", s_reg: " << loc.s_reg_low in DumpRegLocation()
1359 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); in GenInlinedIndexOf()
1811 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); in AppendOpcodeWithConst()
2268 int displacement = SRegOffset(rl_result.s_reg_low); in GenReduceVector()
2623 StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); in GenDalvikArgsRange()
2630 StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k32, kNotVolatile); in GenDalvikArgsRange()
2640 int start_offset = SRegOffset(info->args[last_mapped_in + size_of_the_last_mapped].s_reg_low); in GenDalvikArgsRange()
Dutility_x86.cc394 int displacement = SRegOffset(rl_dest.s_reg_low); in OpMemReg()
423 int displacement = SRegOffset(rl_value.s_reg_low); in OpRegMem()
579 RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); in LoadConstantWide()
/art/compiler/dex/
Dvreg_analysis.cc418 table[i].s_reg_low); in DumpRegLocTable()
429 table[i].s_reg_low); in DumpRegLocTable()
445 loc[i].s_reg_low = i; in InitRegLocations()
453 loc[ct->s_reg_low].location = kLocCompilerTemp; in InitRegLocations()
454 loc[ct->s_reg_low].defined = true; in InitRegLocations()
521 int orig_sreg = reg_location_[i].s_reg_low; in RemapRegLocations()
523 reg_location_[i].s_reg_low = SRegToVReg(orig_sreg); in RemapRegLocations()
Dreg_location.h53 int16_t s_reg_low; // SSA name for low Dalvik word. member
Dmir_optimization.cc265 compiler_temp->s_reg_low = AddNewSReg(compiler_temp->v_reg); in GetNewCompilerTemp()
268 method_sreg_ = compiler_temp->s_reg_low; in GetNewCompilerTemp()
275 compiler_temp->s_reg_low = AddNewSReg(compiler_temp->v_reg); in GetNewCompilerTemp()
283 compiler_temp_high->s_reg_low = compiler_temp->s_reg_low; in GetNewCompilerTemp()
290 int ssa_reg_high = compiler_temp->s_reg_low; in GetNewCompilerTemp()
291 compiler_temp->s_reg_low = AddNewSReg(compiler_temp->v_reg); in GetNewCompilerTemp()
292 int ssa_reg_low = compiler_temp->s_reg_low; in GetNewCompilerTemp()
299 reg_location_[ssa_reg_high].s_reg_low = ssa_reg_low; in GetNewCompilerTemp()
309 int ssa_reg_low = compiler_temp->s_reg_low; in GetNewCompilerTemp()
311 reg_location_[ssa_reg_low].s_reg_low = ssa_reg_low; in GetNewCompilerTemp()
Dmir_graph.h212 int32_t s_reg_low; // SSA name for low Dalvik word. member
/art/compiler/dex/quick/arm/
Dint_arm.cc837 ClobberSReg(rl_src_expected.s_reg_low); in GenInlinedCas()
838 ClobberSReg(GetSRegHi(rl_src_expected.s_reg_low)); in GenInlinedCas()
843 ClobberSReg(rl_src_new_value.s_reg_low); in GenInlinedCas()
844 ClobberSReg(GetSRegHi(rl_src_new_value.s_reg_low)); in GenInlinedCas()
872 ClobberSReg(rl_object.s_reg_low); in GenInlinedCas()
874 ClobberSReg(rl_offset.s_reg_low); in GenInlinedCas()
1201 if ((rl_dest.s_reg_low != rl_src1.s_reg_low && rl_dest.s_reg_low != rl_src2.s_reg_low) && in GenMulLong()
1209 if ((rl_src1.s_reg_low == rl_src2.s_reg_low) || src1_promoted || src2_promoted) { in GenMulLong()
Dfp_arm.cc295 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
303 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
/art/compiler/dex/quick/arm64/
Dtarget_arm64.cc1063 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); in GenDalvikArgsRange()
1071 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, kNotVolatile); in GenDalvikArgsRange()
1073 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k32, in GenDalvikArgsRange()
1085 int start_offset = SRegOffset(info->args[last_mapped_in + 1].s_reg_low); in GenDalvikArgsRange()
Dfp_arm64.cc281 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
289 ClobberSReg(rl_dest.s_reg_low); in GenCmpFP()
Dint_arm64.cc739 ClobberSReg(rl_object.s_reg_low); in GenInlinedCas()
741 ClobberSReg(rl_offset.s_reg_low); in GenInlinedCas()