| /art/runtime/gc/accounting/ |
| D | space_bitmap-inl.h | 110 const size_t shift = CTZ(left_edge); in VisitMarkedRange() local
111 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment); in VisitMarkedRange()
113 left_edge ^= (static_cast<uword>(1)) << shift; in VisitMarkedRange()
123 const size_t shift = CTZ(w); in VisitMarkedRange() local
124 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment); in VisitMarkedRange()
126 w ^= (static_cast<uword>(1)) << shift; in VisitMarkedRange()
149 const size_t shift = CTZ(right_edge); in VisitMarkedRange() local
150 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment); in VisitMarkedRange()
152 right_edge ^= (static_cast<uword>(1)) << shift; in VisitMarkedRange()
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| D | space_bitmap.cc | 115 const size_t shift = CTZ(w); in Walk() local
116 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment); in Walk()
118 w ^= (static_cast<uword>(1)) << shift; in Walk()
163 const size_t shift = CTZ(garbage); in SweepWalk() local
164 garbage ^= (static_cast<uword>(1)) << shift; in SweepWalk()
165 *pb++ = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment); in SweepWalk()
259 const size_t shift = CTZ(w); in InOrderWalk() local
260 mirror::Object* obj = reinterpret_cast<mirror::Object*>(ptr_base + shift * kAlignment); in InOrderWalk()
262 w ^= (static_cast<uword>(1)) << shift; in InOrderWalk()
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| /art/compiler/dex/quick/arm64/ |
| D | utility_arm64.cc | 288 for (int shift = 0; shift < 64; shift += 16) { in GetNumFastHalfWords() local
289 uint16_t halfword = static_cast<uint16_t>(value >> shift); in GetNumFastHalfWords()
422 int shift; in LoadConstantNoClobber() local
425 shift = 0; in LoadConstantNoClobber()
429 shift = 1; in LoadConstantNoClobber()
435 res = NewLIR3(kA64Movn3rdM, r_dest.GetReg(), ~useful_bits, shift); in LoadConstantNoClobber()
437 res = NewLIR3(kA64Movz3rdM, r_dest.GetReg(), useful_bits, shift); in LoadConstantNoClobber()
503 int shift; in LoadConstantWide() local
504 for (shift = 0; shift < 4; shift++) { in LoadConstantWide()
505 uint16_t halfword = static_cast<uint16_t>(uvalue >> (shift << 4)); in LoadConstantWide()
[all …]
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| D | int_arm64.cc | 379 uint32_t shift; member
431 32 + magic_table[lit].shift); in SmallLiteralDivRem()
437 OpRegRegImm(kOpAsr, r_long_mul, r_long_mul, magic_table[lit].shift); in SmallLiteralDivRem()
497 OpRegRegImm(kOpAsr, r_long_mul, r_long_mul, magic_table[lit].shift); in SmallLiteralDivRem64()
502 OpRegRegImm(kOpAsr, r_long_mul, r_long_mul, magic_table[lit].shift); in SmallLiteralDivRem64()
554 int shift = EncodeShift(kA64Lsr, nbits - k); in HandleEasyDivRem64() local
558 OpRegRegRegShift(kOpAdd, t_reg, rl_src.reg, rl_src.reg, shift); in HandleEasyDivRem64()
562 OpRegRegRegShift(kOpAdd, t_reg, rl_src.reg, t_reg, shift); in HandleEasyDivRem64()
567 OpRegRegRegShift(kOpAdd, t_reg, rl_src.reg, rl_src.reg, shift); in HandleEasyDivRem64()
569 OpRegRegRegShift(kOpSub, rl_result.reg, t_reg, rl_src.reg, shift); in HandleEasyDivRem64()
[all …]
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| D | codegen_arm64.h | 367 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
369 int shift);
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| /art/compiler/dex/quick/arm/ |
| D | utility_arm.cc | 239 int shift) { in OpRegRegShift() argument
241 ((shift == 0) && r_dest_src1.Low8() && r_src2.Low8()); in OpRegRegShift()
254 DCHECK_EQ(shift, 0); in OpRegRegShift()
260 else if ((shift == 0) && !r_dest_src1.Low8() && !r_src2.Low8()) in OpRegRegShift()
262 else if ((shift == 0) && r_dest_src1.Low8()) in OpRegRegShift()
264 else if (shift == 0) in OpRegRegShift()
273 DCHECK_EQ(shift, 0); in OpRegRegShift()
284 DCHECK_EQ(shift, 0); in OpRegRegShift()
291 DCHECK_EQ(shift, 0); in OpRegRegShift()
304 DCHECK_EQ(shift, 0); in OpRegRegShift()
[all …]
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| D | int_arm.cc | 468 uint32_t shift; member
521 EncodeShift(kArmAsr, magic_table[lit].shift)); in SmallLiteralDivRem()
527 EncodeShift(kArmAsr, magic_table[lit].shift)); in SmallLiteralDivRem()
563 op->shift = LowestSetBit(lit); in GetEasyMultiplyOp()
569 op->shift = LowestSetBit(lit - 1); in GetEasyMultiplyOp()
575 op->shift = LowestSetBit(lit + 1); in GetEasyMultiplyOp()
580 op->shift = 0; in GetEasyMultiplyOp()
589 ops[1].shift = 0; in GetEasyMultiplyTwoOps()
594 uint32_t shift = LowestSetBit(lit1); in GetEasyMultiplyTwoOps() local
595 if (GetEasyMultiplyOp(lit1 >> shift, &ops[0])) { in GetEasyMultiplyTwoOps()
[all …]
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| D | codegen_arm.h | 167 int shift);
168 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
208 uint32_t shift; member
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| /art/test/083-compiler-regressions/ |
| D | info.txt | 8 2296099 JIT shift bug
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| /art/compiler/utils/arm/ |
| D | constants_arm.h | 260 int Bits(int shift, int count) const { in Bits() argument
261 return (InstructionBits() >> shift) & ((1 << count) - 1); in Bits()
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| D | assembler_arm.h | 50 ShifterOperand(Register rm, Shift shift, uint32_t shift_imm = 0) : type_(kRegister), rm_(rm), in type_()
52 is_rotate_(false), is_shift_(true), shift_(shift), rotate_(0), immed_(shift_imm) { in type_()
56 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), in ShifterOperand() argument
58 is_rotate_(false), is_shift_(true), shift_(shift), rotate_(0), immed_(0) { in ShifterOperand()
207 Address(Register rn, Register rm, Shift shift, uint32_t count, Mode am = Offset) :
209 am_(am), is_immed_offset_(false), shift_(shift) { in rn_()
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| D | assembler_thumb2.cc | 1092 void Thumb2Assembler::EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, bool setcc) { in EmitShift() argument
1094 if (IsHighRegister(rd) || IsHighRegister(rm) || shift == ROR || shift == RRX) { in EmitShift()
1096 switch (shift) { in EmitShift()
1116 switch (shift) { in EmitShift()
1129 void Thumb2Assembler::EmitShift(Register rd, Register rn, Shift shift, Register rm, bool setcc) { in EmitShift() argument
1130 CHECK_NE(shift, RRX); in EmitShift()
1138 switch (shift) { in EmitShift()
1154 switch (shift) { in EmitShift()
1952 static uint8_t ToItMask(ItState s, uint8_t firstcond0, uint8_t shift) { in ToItMask() argument
1954 case kItOmitted: return 1 << shift; in ToItMask()
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| D | assembler_arm.cc | 196 uint32_t shift = shift_; in encodingArm() local
197 if (shift == RRX) { in encodingArm()
199 shift = ROR; in encodingArm()
201 encoding = am_ | static_cast<uint32_t>(rm_) | shift << 5 | offset_ << 7 | B25; in encodingArm()
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| D | assembler_thumb2.h | 419 void EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, bool setcc = false);
420 void EmitShift(Register rd, Register rn, Shift shift, Register rm, bool setcc = false);
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| /art/compiler/dex/quick/x86/ |
| D | int_x86.cc | 525 void X86Mir2Lir::CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long) { in CalculateMagicAndShift() argument
593 shift = (is_long) ? p - 64 : p - 32; in CalculateMagicAndShift()
653 int shift; in GenDivRemLit() local
654 CalculateMagicAndShift((int64_t)imm, magic, shift, false /* is_long */); in GenDivRemLit()
710 if (shift != 0) { in GenDivRemLit()
712 NewLIR2(kX86Sar32RI, rs_r2.GetReg(), shift); in GenDivRemLit()
1847 int shift; in GenDivRemLongLit() local
1848 CalculateMagicAndShift(imm, magic, shift, true /* is_long */); in GenDivRemLongLit()
1894 if (shift != 0) { in GenDivRemLongLit()
1896 OpRegImm(kOpAsr, rs_r2q, shift); in GenDivRemLongLit()
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| D | codegen_x86.h | 720 void CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long);
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| /art/disassembler/ |
| D | disassembler_arm.cc | 149 explicit Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {} in Rm()
150 uint32_t shift; member
155 if (r.shift != 0) { in operator <<()
156 os << "-shift-" << r.shift; // TODO in operator <<()
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| /art/compiler/llvm/ |
| D | intrinsic_func_list.def | 1694 // the llvm shift operators. For 32-bit shifts, the shift count is constrained
1696 // Further, the shift count for Long shifts in Dalvik is 32 bits, while
1697 // llvm requires a 64-bit shift count. For GBC, we represent shifts as an
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| /art/runtime/arch/mips/ |
| D | quick_entrypoints_mips.S | 499 srl $t0, $t0, 4 # shift the frame size right 4
500 sll $t0, $t0, 4 # shift the frame size left 4 to align to 16 bytes
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