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Searched refs:Valid (Results 1 – 21 of 21) sorted by relevance

/art/compiler/dex/
Dreg_storage.h142 constexpr bool Valid() const { in Valid() function
168 DCHECK_CONSTEXPR(Valid(), , false) in IsFloat()
174 DCHECK_CONSTEXPR(Valid(), , false) in IsDouble()
180 DCHECK_CONSTEXPR(Valid(), , false) in IsSingle()
211 return Valid() ? (reg_ & kRegValMask) : kInvalidRegVal; in GetReg()
216 DCHECK(Valid()); in SetReg()
/art/test/072-precise-gc/
Dexpected.txt1 Valid refs: 0
/art/compiler/utils/
Ddex_cache_arrays_layout.h42 bool Valid() const { in Valid() function
/art/compiler/dex/quick/
Dralloc_util.cc58 used_storage_ = r.Valid() ? ~storage_mask_ : storage_mask_; in RegisterInfo()
477 if (!reg.Valid() && ((reg_class == kAnyReg) || (reg_class == kFPReg))) { in AllocLiveReg()
480 if (!reg.Valid() && (reg_class != kFPReg)) { in AllocLiveReg()
488 if (reg.Valid()) { in AllocLiveReg()
492 if (high_reg.Valid()) { in AllocLiveReg()
500 if (reg.Valid() && (wide != GetRegInfo(reg)->IsWide())) { in AllocLiveReg()
505 if (reg.Valid()) { in AllocLiveReg()
998 if (reg.Valid()) { in UpdateLoc()
1023 if (reg.Valid()) { in UpdateLocWide()
1426 if (!reg.Valid()) { in DoPromotion()
[all …]
Dmir_to_lir.cc110 if (reg_arg.Valid()) { in LockArg()
138 if (reg_arg.Valid() && wide && (reg_arg.GetWideKind() == kNotWide)) { in LoadArg()
145 if (!reg_arg.Valid()) { in LoadArg()
188 if (reg_arg.Valid() && rl_dest.wide && (reg_arg.GetWideKind() == kNotWide)) { in LoadArgDirect()
195 if (!reg_arg.Valid()) { in LoadArgDirect()
210 if (reg_arg.Valid()) { in SpillArg()
222 if (reg_arg.Valid()) { in UnspillArg()
1367 if (rs.Valid()) { in CheckRegStorageImpl()
1434 if (reg.Valid()) { in Initialize()
Dgen_invoke.cc93 if (r_tgt.Valid()) { in CallHelper()
448 if (t_loc->wide && reg.Valid() && !reg.Is64Bit()) { in FlushIns()
453 if (reg.Valid()) { in FlushIns()
799 if (!reg.Valid()) { in GenDalvikArgs()
842 if (reg.Valid()) { in GenDalvikArgs()
Dgen_loadstore.cc354 DCHECK(r_hint.Valid()); in LoadCurrMethodWithHint()
Dcodegen_util.cc333 DCHECK(val_reg.Valid()); in MarkGCCard()
1350 DCHECK(loc.reg.Valid()); in NarrowRegLoc()
Dgen_common.cc2184 if (key_temp.Valid()) { in GenSmallPackedSwitch()
/art/compiler/dex/quick/arm/
Dfp_arm.cc173 DCHECK(src_low.Valid()); in GenConversion()
175 DCHECK(src_high.Valid()); in GenConversion()
197 DCHECK(src_low.Valid()); in GenConversion()
199 DCHECK(src_high.Valid()); in GenConversion()
Dint_arm.cc1096 return dex_cache_arrays_layout_.Valid(); in CanUseOpPcRelDexCacheArrayLoad()
1118 if (dex_cache_arrays_base_reg_.Valid()) { in OpPcRelDexCacheArrayLoad()
1276 bool dest_promoted = rl_dest.location == kLocPhysReg && rl_dest.reg.Valid() && in GenMulLong()
1307 DCHECK(res_hi.Valid()); in GenMulLong()
1308 DCHECK(res_lo.Valid()); in GenMulLong()
1316 DCHECK(!res_hi.Valid()); in GenMulLong()
1324 DCHECK(res_hi.Valid()); in GenMulLong()
1325 DCHECK(res_lo.Valid()); in GenMulLong()
Dutility_arm.cc888 r_ptr = r_work.Valid() ? r_work : AllocTemp(); in LoadStoreUsingInsnWithOffsetImm8Shl2()
899 if ((displacement & ~kOffsetMask) != 0 && !r_work.Valid()) { in LoadStoreUsingInsnWithOffsetImm8Shl2()
1195 if (r_temp_high.Valid()) { in StoreBaseDisp()
1299 DCHECK(!dex_cache_arrays_base_reg_.Valid() || !dex_cache_arrays_base_reg_.IsFloat()); in DoPromotion()
Dcall_arm.cc517 if (dex_cache_arrays_base_reg_.Valid()) { in GenEntrySequence()
Dtarget_arm.cc875 if (res.Valid()) { in AllocPreservedDouble()
/art/compiler/dex/quick/x86/
Dutility_x86.cc578 } else if (pc_rel_base_reg_.Valid() || cu_->target64) { in LoadConstantWide()
647 bool is_array = r_index.Valid(); in LoadBaseIndexedDisp()
796 bool is_array = r_index.Valid(); in StoreBaseIndexedDisp()
1155 DCHECK(!pc_rel_base_reg_.Valid() || !pc_rel_base_reg_.IsFloat()); in DoPromotion()
Dint_x86.cc243 if (temp_reg.Valid()) { in GenSelectConst32()
724 DCHECK(numerator_reg.Valid()); in GenDivRemLit()
727 DCHECK(numerator_reg.Valid()); in GenDivRemLit()
752 DCHECK(numerator_reg.Valid()); in GenDivRemLit()
1106 return rl.reg.Valid() && rl.reg.GetReg() == reg.GetReg() && (pMir2Lir->IsLive(reg) || rl.home); in IsInReg()
1397 return dex_cache_arrays_layout_.Valid(); in CanUseOpPcRelDexCacheArrayLoad()
1411 if (pc_rel_base_reg_.Valid()) { in GetPcAndAnchor()
1419 RegStorage r_pc = r_tmp.Valid() ? r_tmp : AllocTempRef(); in GetPcAndAnchor()
2270 DCHECK(numerator_reg.Valid()); in GenDivRemLongLit()
2273 DCHECK(numerator_reg.Valid()); in GenDivRemLongLit()
[all …]
Dcall_x86.cc244 if (pc_rel_base_reg_.Valid()) { in GenEntrySequence()
Dassemble_x86.cc2022 if (pc_rel_base_reg_.Valid() && !pc_rel_base_reg_used_) { in AssembleLIR()
/art/compiler/dex/quick/arm64/
Dint_arm64.cc170 if (!right_op.Valid()) { in GenSelect()
178 DCHECK(left_op.Valid() && right_op.Valid()); in GenSelect()
186 DCHECK(rs_dest.Valid()); in GenSelectConst32()
947 return dex_cache_arrays_layout_.Valid(); in CanUseOpPcRelDexCacheArrayLoad()
Dtarget_arm64.cc827 if (result.Valid()) { in GetNextReg()
836 if (result.Valid()) { in GetNextReg()
/art/compiler/
Dimage_writer.cc313 DCHECK(layout.Valid()); in PrepareDexCacheArraySlots()