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Searched refs:BaseReg (Results 1 – 25 of 47) sorted by relevance

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/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp127 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
134 (BaseReg != 0 && !isARMLowRegister(BaseReg)); in emitThumbRegPlusImmInReg()
146 assert(BaseReg == ARM::SP && "Unexpected!"); in emitThumbRegPlusImmInReg()
170 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
172 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
183 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate() argument
214 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
226 if (BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
232 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
235 } else if (isARMLowRegister(BaseReg)) { in emitThumbRegPlusImmediate()
[all …]
DThumb2InstrInfo.cpp222 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
225 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
227 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
237 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
259 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
266 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
277 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
280 .addReg(BaseReg).setMIFlags(MIFlags)); in emitT2RegPlusImmediate()
281 BaseReg = ARM::SP; in emitT2RegPlusImmediate()
286 if (BaseReg == ARM::SP) { in emitT2RegPlusImmediate()
[all …]
DARMBaseRegisterInfo.h142 unsigned BaseReg, int FrameIdx,
144 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
146 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
DARMBaseRegisterInfo.cpp568 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
583 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
585 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
592 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
611 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
614 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
620 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal() argument
664 NumBits = (BaseReg == ARM::SP ? 8 : 5); in isFrameOffsetLegal()
DARMLoadStoreOptimizer.cpp1454 unsigned BaseReg, bool BaseKill, bool BaseUndef, in InsertLDR_STR() argument
1462 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1468 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef)); in InsertLDR_STR()
1480 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1487 bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3(); in FixInvalidRegPairOp()
1517 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1524 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
1548 (TRI->regsOverlap(EvenReg, BaseReg))) { in FixInvalidRegPairOp()
1549 assert(!TRI->regsOverlap(OddReg, BaseReg)); in FixInvalidRegPairOp()
1552 BaseReg, false, BaseUndef, false, OffUndef, in FixInvalidRegPairOp()
[all …]
DThumb2SizeReduction.cpp418 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
419 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA) in ReduceLoadStore()
426 if (MI->getOperand(i).getReg() == BaseReg) { in ReduceLoadStore()
440 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
441 if (BaseReg != ARM::SP) in ReduceLoadStore()
454 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
455 if (BaseReg == ARM::SP && in ReduceLoadStore()
460 } else if (!isARMLowRegister(BaseReg) || in ReduceLoadStore()
DARMBaseInstrInfo.h86 RegSubRegPair &BaseReg,
460 unsigned DestReg, unsigned BaseReg, int NumBytes,
466 unsigned DestReg, unsigned BaseReg, int NumBytes,
471 unsigned DestReg, unsigned BaseReg,
DThumbRegisterInfo.h52 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
/external/llvm/lib/CodeGen/
DLocalStackSlotAllocation.cpp255 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg() argument
264 return TRI->isFrameOffsetLegal(MI, BaseReg, Offset); in lookupCandidateBaseReg()
330 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
366 if (UsedBaseReg && lookupCandidateBaseReg(BaseReg, BaseOffset, in insertFrameReferenceRegisters()
369 DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n"); in insertFrameReferenceRegisters()
387 BaseReg, BaseOffset, FrameSizeAdjust, in insertFrameReferenceRegisters()
396 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
398 DEBUG(dbgs() << " Materializing base register " << BaseReg << in insertFrameReferenceRegisters()
404 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
415 assert(BaseReg != 0 && "Unable to allocate virtual base register!"); in insertFrameReferenceRegisters()
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DCodeGenPrepare.cpp1546 Value *BaseReg; member
1548 ExtAddrMode() : BaseReg(nullptr), ScaledReg(nullptr) {} in ExtAddrMode()
1553 return (BaseReg == O.BaseReg) && (ScaledReg == O.ScaledReg) && in operator ==()
1582 if (BaseReg) { in print()
1585 BaseReg->printAsOperand(OS, /*PrintType=*/false); in print()
2747 AddrMode.BaseReg = AddrInst->getOperand(0); in MatchOperationAddr()
2760 AddrMode.BaseReg = AddrInst->getOperand(0); in MatchOperationAddr()
2894 AddrMode.BaseReg = Addr; in MatchAddr()
2899 AddrMode.BaseReg = nullptr; in MatchAddr()
3052 Value *BaseReg = AMAfter.BaseReg, *ScaledReg = AMAfter.ScaledReg; in IsProfitableToFoldIntoAddressingMode() local
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/external/llvm/lib/Target/AArch64/
DAArch64LoadStoreOptimizer.cpp501 unsigned BaseReg = FirstMI->getOperand(1).getReg(); in findMatchingInsn() local
509 if (FirstMI->modifiesRegister(BaseReg, TRI)) in findMatchingInsn()
556 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) || in findMatchingInsn()
630 if (ModifiedRegs[BaseReg]) in findMatchingInsn()
723 static bool isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg, in isMatchingUpdateInsn() argument
742 if (MI->getOperand(0).getReg() == BaseReg && in isMatchingUpdateInsn()
743 MI->getOperand(1).getReg() == BaseReg && in isMatchingUpdateInsn()
764 unsigned BaseReg = MemMI->getOperand(1).getReg(); in findMatchingUpdateInsnForward() local
770 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnForward()
796 if (isMatchingUpdateInsn(MI, BaseReg, Value)) in findMatchingUpdateInsnForward()
[all …]
DAArch64StorePairSuppress.cpp143 unsigned BaseReg; in runOnMachineFunction() local
145 if (TII->getLdStBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) { in runOnMachineFunction()
146 if (PrevBaseReg == BaseReg) { in runOnMachineFunction()
155 PrevBaseReg = BaseReg; in runOnMachineFunction()
DAArch64RegisterInfo.h75 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
77 void materializeFrameBaseRegister(MachineBasicBlock *MBB, unsigned BaseReg,
80 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
DAArch64RegisterInfo.cpp320 unsigned BaseReg, in isFrameOffsetLegal() argument
331 unsigned BaseReg, in materializeFrameBaseRegister() argument
343 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
346 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
352 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
364 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); in resolveFrameIndex()
DAArch64InstrInfo.h93 bool getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
97 bool getLdStBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp255 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
264 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
268 unsigned getBaseReg() { return BaseReg; } in getBaseReg()
359 if (!BaseReg) { in onPlus()
360 BaseReg = TmpReg; in onPlus()
396 if (!BaseReg) { in onMinus()
397 BaseReg = TmpReg; in onMinus()
574 if (!BaseReg) { in onRBrac()
575 BaseReg = TmpReg; in onRBrac()
681 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
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DX86Operand.h52 unsigned BaseReg; member
114 return Mem.BaseReg; in getMemBaseReg()
483 Res->Mem.BaseReg = 0;
497 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
502 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
510 Res->Mem.BaseReg = BaseReg;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
64 if (is16BitMode(STI) && BaseReg.getReg() == 0 && in Is16BitMemOperand()
67 if ((BaseReg.getReg() != 0 && in Is16BitMemOperand()
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
229 if ((BaseReg.getReg() != 0 && in Is32BitMemOperand()
230 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || in Is32BitMemOperand()
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
244 if ((BaseReg.getReg() != 0 && in Is64BitMemOperand()
245 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || in Is64BitMemOperand()
[all …]
/external/llvm/lib/Target/X86/InstPrinter/
DX86ATTInstPrinter.cpp187 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
202 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
209 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
211 if (BaseReg.getReg()) in printMemReference()
DX86IntelInstPrinter.cpp159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
174 if (BaseReg.getReg()) { in printMemReference()
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.h126 unsigned BaseReg, int FrameIdx,
128 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
130 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
DPPCRegisterInfo.cpp972 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
986 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); in materializeFrameBaseRegister()
988 BuildMI(*MBB, Ins, DL, MCID, BaseReg) in materializeFrameBaseRegister()
992 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
1001 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); in resolveFrameIndex()
1012 MRI.constrainRegClass(BaseReg, in resolveFrameIndex()
1017 unsigned BaseReg, in isFrameOffsetLegal() argument
/external/llvm/lib/Target/X86/
DX86AsmPrinter.cpp238 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printLeaMemReference() local
243 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference()
245 BaseReg.getReg() == X86::RIP) in printLeaMemReference()
303 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printIntelMemReference() local
318 if (BaseReg.getReg()) { in printIntelMemReference()
336 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printIntelMemReference()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
123 emitMask(BaseReg, LoadStoreStackMaskReg, STI); in sandboxLoadStoreStackChange()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h792 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister() argument
800 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex() argument
807 virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal() argument

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