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/external/clang/tools/clang-format-vs/
DClangFormat.sln4 …4F79EFBC}") = "ClangFormat", "ClangFormat\ClangFormat.csproj", "{7FD1783E-2D31-4D05-BF23-6EBE1B42B…
12 {7FD1783E-2D31-4D05-BF23-6EBE1B42B608}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
13 {7FD1783E-2D31-4D05-BF23-6EBE1B42B608}.Debug|Any CPU.Build.0 = Debug|Any CPU
14 {7FD1783E-2D31-4D05-BF23-6EBE1B42B608}.Release|Any CPU.ActiveCfg = Release|Any CPU
15 {7FD1783E-2D31-4D05-BF23-6EBE1B42B608}.Release|Any CPU.Build.0 = Release|Any CPU
/external/libhevc/common/arm/
Dihevc_sao_band_offset_luma.s100 VDUP.8 D31,r11 @band_pos
118 … VADD.I8 D5,D1,D31 @band_table.val[0] = vadd_u8(band_table.val[0], band_pos)
121 … VADD.I8 D6,D2,D31 @band_table.val[1] = vadd_u8(band_table.val[1], band_pos)
124 … VADD.I8 D7,D3,D31 @band_table.val[2] = vadd_u8(band_table.val[2], band_pos)
127 … VADD.I8 D8,D4,D31 @band_table.val[3] = vadd_u8(band_table.val[3], band_pos)
200 VSUB.I8 D14,D13,D31 @vsub_u8(au1_cur_row, band_pos)
203 VSUB.I8 D16,D15,D31 @vsub_u8(au1_cur_row, band_pos)
206 VSUB.I8 D18,D17,D31 @vsub_u8(au1_cur_row, band_pos)
209 VSUB.I8 D20,D19,D31 @vsub_u8(au1_cur_row, band_pos)
Dihevc_sao_band_offset_chroma.s110 VDUP.8 D31,r6 @band_pos_u
124 …VADD.I8 D5,D1,D31 @band_table_u.val[0] = vadd_u8(band_table_u.val[0], sao_ba…
127 …VADD.I8 D6,D2,D31 @band_table_u.val[1] = vadd_u8(band_table_u.val[1], sao_ba…
130 …VADD.I8 D7,D3,D31 @band_table_u.val[2] = vadd_u8(band_table_u.val[2], sao_ba…
133 …VADD.I8 D8,D4,D31 @band_table_u.val[3] = vadd_u8(band_table_u.val[3], sao_ba…
290 VSUB.I8 D7,D5,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
296 VSUB.I8 D15,D13,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
302 VSUB.I8 D19,D17,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
308 VSUB.I8 D23,D21,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
344 VSUB.I8 D7,D5,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
[all …]
Dihevc_sao_edge_offset_class1.s131 VLD1.8 D31,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
149 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
214 VMOVN.I16 D31,Q14 @II vmovn_s16(pi2_tmp_cur_row.val[1])
249 VMOVN.I16 D31,Q14 @vmovn_s16(pi2_tmp_cur_row.val[1])
291 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
Dihevc_sao_edge_offset_class1_chroma.s136 VLD1.8 D31,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
154 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
227 VMOVN.I16 D31,Q14 @II vmovn_s16(pi2_tmp_cur_row.val[1])
267 VMOVN.I16 D31,Q14 @vmovn_s16(pi2_tmp_cur_row.val[1])
309 VLD1.8 D31,[r6] @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
Dihevc_sao_edge_offset_class0_chroma.s157 VLD1.8 D31,[r12] @II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)
258 …VMOVL.U8 Q15,D31 @II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vmovl_u…
320 VLD1.8 D31,[r12] @II pu1_cur_row = vld1q_u8(pu1_src_cpy)
Dihevc_sao_edge_offset_class0.s231 … VTBL.8 D31,{D11},D29 @II offset = vtbl1_s8(offset_tbl, vget_high_s8(edge_idx))
244 …VADDW.S8 Q14,Q14,D31 @II pi2_tmp_cur_row.val[1] = vaddw_s8(pi2_tmp_cur_row.val[…
Dihevc_sao_edge_offset_class2.s341 VLD1.8 D31,[r11] @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
Dihevc_sao_edge_offset_class3.s357 VLD1.8 D31,[r2] @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
Dihevc_sao_edge_offset_class2_chroma.s448 VLD1.8 D31,[r11] @III pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s166 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
222 VADDW.U8 Q10,Q4,D31 @//Q10 - HAS Y + B
223 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
224 VADDW.U8 Q12,Q6,D31 @//Q12 - HAS Y + G
269 VLD2.8 {D30,D31},[R0]! @//D0 - Y0,Y2,Y4,Y6,Y8,Y10,Y12,Y14 row 1
353 VADDW.U8 Q10,Q4,D31 @//Q10 - HAS Y + B
354 VADDW.U8 Q11,Q5,D31 @//Q11 - HAS Y + R
355 VADDW.U8 Q12,Q6,D31 @//Q12 - HAS Y + G
/external/harfbuzz_ng/test/shaping/tests/
Dindic-old-spec.tests2 fonts/sha1sum/270b89df543a7e48e206a2d830c0e10e5265c630.ttf:U+0D38,U+0D4D,U+0D31,U+0D4D,U+0D31,U+0D4…
/external/llvm/test/MC/MachO/
Dx86_64-symbols.s98 D31: label
Dx86_32-symbols.s98 D31: label
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td134 def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
155 def Q15 : ARMReg<15, "q15", [D30, D31]>;
286 // Allocate non-VFP2 registers D16-D31 first.
329 // Allocate starting at non-VFP2 registers D16-D31 first.
DARMBaseRegisterInfo.cpp147 assert(ARM::D31 == ARM::D16 + 15); in getReservedRegs()
DARMFrameLowering.cpp602 if ((Reg >= ARM::D0 && Reg <= ARM::D31) && in emitPrologue()
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td163 def D31 : SparcReg<31, "F62">;
181 def Q15 : Rq<29, "F60", [D30, D31]>;
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h142 case AArch64::D31: return AArch64::B31; in getBRegFromDReg()
182 case AArch64::B31: return AArch64::D31; in getDRegFromBReg()
/external/llvm/lib/Target/AArch64/
DAArch64PBQPRegAlloc.cpp79 case AArch64::D31: in isOdd()
DAArch64RegisterInfo.td347 def D31 : AArch64Reg<31, "d31", [S31], ["v31", ""]>, DwarfRegAlias<B31>;
382 def Q31 : AArch64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp94 SP::D14, SP::D30, SP::D15, SP::D31 };
/external/valgrind/memcheck/
Dmc_machine.c905 if (o >= GOF(D31) && o+sz <= GOF(D31)+SZB(D31)) return GOF(D31); in get_otrack_shadow_offset_wrk()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp119 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp283 AArch64::D30, AArch64::D31

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