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Searched refs:DestReg (Results 1 – 25 of 79) sorted by relevance

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/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp42 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
48 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
52 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
53 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
66 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
100 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
104 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
105 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()
108 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
109 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
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DThumbRegisterInfo.cpp64 DebugLoc dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
84 DebugLoc dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, in emitLoadConstPool() argument
110 assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) && in emitLoadConstPool()
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
127 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
133 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
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DThumb2InstrInfo.cpp114 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
169 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
185 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
195 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in loadRegFromStackSlot()
198 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
199 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
203 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
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DARMBaseInstrInfo.cpp696 unsigned DestReg, bool KillSrc, in copyFromCPSR() argument
703 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg); in copyFromCPSR()
739 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
741 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
745 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
750 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
760 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP()) in copyPhysReg()
762 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
766 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
780 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
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DARMBaseInstrInfo.h163 unsigned DestReg, bool KillSrc,
167 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
178 unsigned DestReg, int FrameIndex,
185 unsigned DestReg, unsigned SubIdx,
460 unsigned DestReg, unsigned BaseReg, int NumBytes,
466 unsigned DestReg, unsigned BaseReg, int NumBytes,
471 unsigned DestReg, unsigned BaseReg,
/external/llvm/lib/Target/Hexagon/
DHexagonSplitConst32AndConst64.cpp87 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
90 TII->get(Hexagon::A2_tfrsi), DestReg).addOperand(Symbol); in runOnMachineFunction()
99 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
103 TII->get(Hexagon::LO), DestReg).addOperand(Symbol); in runOnMachineFunction()
105 TII->get(Hexagon::HI), DestReg).addOperand(Symbol); in runOnMachineFunction()
114 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
127 TII->get(Hexagon::A2_tfrsi), DestReg).addImm(ImmValue); in runOnMachineFunction()
133 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
145 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg); in runOnMachineFunction()
146 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg); in runOnMachineFunction()
DHexagonCopyToCombine.cpp93 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
96 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
99 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
102 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
121 unsigned DestReg = MI->getOperand(0).getReg(); in isCombinableInstType() local
123 return Hexagon::IntRegsRegClass.contains(DestReg) && in isCombinableInstType()
134 unsigned DestReg = Op0.getReg(); in isCombinableInstType() local
143 return Hexagon::IntRegsRegClass.contains(DestReg) && in isCombinableInstType()
158 unsigned DestReg = MI->getOperand(0).getReg(); in isCombinableInstType() local
159 return Hexagon::IntRegsRegClass.contains(DestReg); in isCombinableInstType()
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DHexagonInstrInfo.cpp429 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
431 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
432 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg); in copyPhysReg()
435 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
436 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg); in copyPhysReg()
439 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
442 DestReg).addReg(SrcReg).addReg(SrcReg); in copyPhysReg()
445 if (Hexagon::DoubleRegsRegClass.contains(DestReg) && in copyPhysReg()
448 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { in copyPhysReg()
450 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg, in copyPhysReg()
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/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp113 bool emitCmp(unsigned DestReg, const CmpInst *CI);
121 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
124 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
126 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
128 unsigned DestReg);
130 unsigned DestReg);
299 unsigned DestReg = createResultReg(RC); in materializeFP() local
301 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
302 return DestReg; in materializeFP()
305 unsigned DestReg = createResultReg(RC); in materializeFP() local
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DMipsSEInstrInfo.cpp81 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
115 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
117 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
119 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
120 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
121 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
122 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
123 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
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DMips16InstrInfo.cpp63 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
67 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
70 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
74 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
78 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
86 if (DestReg) in copyPhysReg()
87 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
113 unsigned DestReg, int FI, in loadRegFromStack() argument
125 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) in loadRegFromStack()
DMipsInstrInfo.h100 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
103 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); in loadRegFromStackSlot()
115 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp35 unsigned DestReg, unsigned SrcReg, bool KillSrc) const { in copyPhysReg() argument
37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg()
44 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg) in copyPhysReg()
47 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg) in copyPhysReg()
50 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg) in copyPhysReg()
53 BuildMI(MBB, I, DL, get(NVPTX::IMOV16rr), DestReg) in copyPhysReg()
56 BuildMI(MBB, I, DL, get(NVPTX::IMOV64rr), DestReg) in copyPhysReg()
59 BuildMI(MBB, I, DL, get(NVPTX::FMOV64rr), DestReg) in copyPhysReg()
67 unsigned &DestReg) const { in isMoveInstr()
82 DestReg = dest.getReg(); in isMoveInstr()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp282 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
294 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
295 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
297 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
298 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
300 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
302 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
310 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
313 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
337 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); in copyPhysReg()
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/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp1503 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, in forwardCopyWillClobberTuple() argument
1507 return ((DestReg - SrcReg) & 0x1f) < NumRegs; in forwardCopyWillClobberTuple()
1512 unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, in copyPhysRegTuple() argument
1517 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyPhysRegTuple()
1530 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
1538 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
1540 if (AArch64::GPR32spRegClass.contains(DestReg) && in copyPhysReg()
1544 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { in copyPhysReg()
1548 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32, in copyPhysReg()
1562 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg) in copyPhysReg()
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DAArch64A57FPLoadBalancing.cpp620 unsigned DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
623 << TRI->getName(DestReg) << " at " << *MI); in scanInstruction()
625 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
626 ActiveChains[DestReg] = G.get(); in scanInstruction()
633 unsigned DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
638 if (DestReg != AccumReg) in scanInstruction()
653 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
655 if (DestReg != AccumReg) { in scanInstruction()
656 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
668 << TRI->getName(DestReg) << "\n"); in scanInstruction()
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DAArch64InstrInfo.h113 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
117 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
127 MachineBasicBlock::iterator MBBI, unsigned DestReg,
199 DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
/external/llvm/lib/Target/R600/
DR600MachineScheduler.cpp275 unsigned DestReg = MI->getOperand(0).getReg(); in getAluKind() local
276 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) || in getAluKind()
277 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass)) in getAluKind()
279 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass)) in getAluKind()
281 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass)) in getAluKind()
283 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass)) in getAluKind()
285 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass)) in getAluKind()
364 unsigned DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
371 MO.getReg() == DestReg) in AssignSlot()
377 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass); in AssignSlot()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp636 unsigned DestReg, in insertSelect() argument
694 BuildMI(MBB, MI, dl, get(OpCode), DestReg) in insertSelect()
728 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
733 if (PPC::F8RCRegClass.contains(DestReg) && in copyPhysReg()
736 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
741 DestReg = SuperReg; in copyPhysReg()
742 } else if (PPC::VRRCRegClass.contains(DestReg) && in copyPhysReg()
745 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass); in copyPhysReg()
750 DestReg = SuperReg; in copyPhysReg()
752 PPC::VSRCRegClass.contains(DestReg)) { in copyPhysReg()
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/external/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp36 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
38 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
65 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
73 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp120 unsigned DestReg = MI->getOperand(0).getReg(); in expandRIEPseudo() local
122 bool DestIsHigh = isHighReg(DestReg); in expandRIEPseudo()
128 DestReg, SrcReg, SystemZ::LR, 32, in expandRIEPseudo()
131 MI->getOperand(1).setReg(DestReg); in expandRIEPseudo()
164 DebugLoc DL, unsigned DestReg, in emitGRX32Move() argument
168 bool DestIsHigh = isHighReg(DestReg); in emitGRX32Move()
177 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg) in emitGRX32Move()
182 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
183 .addReg(DestReg, RegState::Undef) in emitGRX32Move()
555 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
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/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h247 unsigned DestReg) { in BuildMI() argument
249 .addReg(DestReg, RegState::Define); in BuildMI()
260 unsigned DestReg) { in BuildMI() argument
264 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
271 unsigned DestReg) { in BuildMI() argument
275 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
282 unsigned DestReg) { in BuildMI() argument
285 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
289 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
346 unsigned DestReg) { in BuildMI() argument
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/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); in copyPhysReg()
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in copyPhysReg()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp67 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
86 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
93 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
103 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp343 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
345 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); in copyPhysReg()
349 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
356 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
360 if (DestReg == XCore::SP && GRSrc) { in copyPhysReg()
394 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
408 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()

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