Home
last modified time | relevance | path

Searched refs:DstVT (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp28 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) { in getZeroExtensionTypes() argument
38 DstVT = MVT::v8i16; in getZeroExtensionTypes()
43 DstVT = MVT::v16i16; in getZeroExtensionTypes()
50 DstVT = MVT::v4i32; in getZeroExtensionTypes()
55 DstVT = MVT::v8i32; in getZeroExtensionTypes()
62 DstVT = MVT::v2i64; in getZeroExtensionTypes()
67 DstVT = MVT::v4i64; in getZeroExtensionTypes()
75 DstVT = MVT::v4i32; in getZeroExtensionTypes()
80 DstVT = MVT::v8i32; in getZeroExtensionTypes()
87 DstVT = MVT::v2i64; in getZeroExtensionTypes()
[all …]
/external/llvm/lib/Transforms/Scalar/
DScalarizer.cpp482 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy()); in visitBitCastInst() local
484 if (!DstVT || !SrcVT) in visitBitCastInst()
487 unsigned DstNumElems = DstVT->getNumElements(); in visitBitCastInst()
496 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(), in visitBitCastInst()
502 Type *MidTy = VectorType::get(DstVT->getElementType(), FanOut); in visitBitCastInst()
528 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(), in visitBitCastInst()
/external/llvm/lib/Target/X86/
DX86SelectionDAGInfo.cpp277 EVT DstVT = Dst.getValueType(); in EmitTargetCodeForMemcpy() local
281 DAG.getNode(ISD::ADD, dl, DstVT, Dst, in EmitTargetCodeForMemcpy()
282 DAG.getConstant(Offset, DstVT)), in EmitTargetCodeForMemcpy()
DX86FastISel.cpp95 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
522 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend() argument
525 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, in X86FastEmitExtend()
1017 EVT DstVT = VA.getValVT(); in X86SelectRet() local
1019 if (SrcVT != DstVT) { in X86SelectRet()
1026 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); in X86SelectRet()
1036 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, in X86SelectRet()
1285 EVT DstVT = TLI.getValueType(I->getType()); in X86SelectZExt() local
1286 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1304 if (DstVT == MVT::i64) { in X86SelectZExt()
[all …]
DX86ISelDAGToDAG.cpp506 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
509 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
517 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
535 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. in PreprocessISelDAG()
537 MemVT = SrcIsSSE ? SrcVT : DstVT; in PreprocessISelDAG()
547 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, in PreprocessISelDAG()
DX86ISelLowering.cpp11751 MVT DstVT = Op.getSimpleValueType(); in LowerUINT_TO_FP() local
11752 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) in LowerUINT_TO_FP()
11756 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32) in LowerUINT_TO_FP()
11822 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); in LowerUINT_TO_FP()
16880 MVT DstVT = Op.getSimpleValueType(); in LowerBITCAST() local
16884 if (DstVT != MVT::f64) in LowerBITCAST()
16912 assert((DstVT == MVT::i64 || in LowerBITCAST()
16913 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && in LowerBITCAST()
16916 if (SrcVT==MVT::i64 && DstVT.isVector()) in LowerBITCAST()
16918 if (DstVT==MVT::i64 && SrcVT.isVector()) in LowerBITCAST()
[all …]
DX86InstrSSE.td3965 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3974 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3981 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3989 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3995 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4005 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4012 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6816 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6826 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6833 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp964 MVT DstVT; in SelectIToFP() local
966 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
969 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
997 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT()) in SelectIToFP()
1019 if (DstVT == MVT::f32) in SelectIToFP()
1073 MVT DstVT, SrcVT; in SelectFPToI() local
1075 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1078 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1082 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT()) in SelectFPToI()
1114 if (DstVT == MVT::i32) in SelectFPToI()
[all …]
/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp402 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT, SmallVectorImpl<int> &Mask) { in DecodeZeroExtendMask() argument
403 unsigned NumDstElts = DstVT.getVectorNumElements(); in DecodeZeroExtendMask()
405 unsigned DstScalarBits = DstVT.getScalarSizeInBits(); in DecodeZeroExtendMask()
DX86ShuffleDecode.h94 void DecodeZeroExtendMask(MVT SrcVT, MVT DstVT,
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1228 EVT DstVT = TLI.getValueType(I->getType()); in selectCast() local
1230 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1231 !DstVT.isSimple()) in selectCast()
1236 if (!TLI.isTypeLegal(DstVT)) in selectCast()
1250 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1278 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local
1286 if (SrcVT == DstVT) { in selectBitCast()
1288 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
1299 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill); in selectBitCast()
1565 EVT DstVT = TLI.getValueType(I->getType()); in selectOperator() local
[all …]
DLegalizeIntegerTypes.cpp2735 EVT DstVT = N->getValueType(0); in ExpandIntOp_SINT_TO_FP() local
2736 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); in ExpandIntOp_SINT_TO_FP()
2739 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first; in ExpandIntOp_SINT_TO_FP()
2839 EVT DstVT = N->getValueType(0); in ExpandIntOp_UINT_TO_FP() local
2845 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT); in ExpandIntOp_UINT_TO_FP()
2849 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP()
2896 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), in ExpandIntOp_UINT_TO_FP()
2901 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); in ExpandIntOp_UINT_TO_FP()
2905 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT); in ExpandIntOp_UINT_TO_FP()
2908 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first; in ExpandIntOp_UINT_TO_FP()
DDAGCombiner.cpp5438 EVT DstVT = N->getValueType(0); in CombineExtLoad() local
5468 !N0.hasOneUse() || LN0->isVolatile() || !DstVT.isVector() || in CombineExtLoad()
5469 !DstVT.isPow2VectorType() || !TLI.isVectorLoadExtDesirable(SDValue(N, 0))) in CombineExtLoad()
5481 EVT SplitDstVT = DstVT; in CombineExtLoad()
5493 DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements(); in CombineExtLoad()
5517 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); in CombineExtLoad()
/external/llvm/lib/Target/R600/
DSIInstrInfo.td912 field ValueType DstVT = ArgVT[0];
916 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1303 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1305 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1316 [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
1318 [(set P.DstVT:$dst, (node P.Src0VT:$src0))]),
1340 [(set P.DstVT:$dst,
1344 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
1355 [(set P.DstVT:$dst,
1359 [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
[all …]
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3577 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3579 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3634 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3637 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3642 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3645 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3650 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3652 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3654 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3656 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
[all …]
DMipsFastISel.cpp900 MVT DstVT, SrcVT; in selectFPToInt() local
905 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt()
908 if (DstVT != MVT::i32) in selectFPToInt()
DMipsDSPInstrInfo.td1278 class BitconvertPat<ValueType DstVT, ValueType SrcVT, RegisterClass DstRC,
1280 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp970 EVT DstVT = N->getValueType(0); in SelectIndexedLoad() local
993 DstVT = MVT::i32; in SelectIndexedLoad()
997 if (DstVT == MVT::i64) in SelectIndexedLoad()
1003 InsertTo64 = DstVT == MVT::i64; in SelectIndexedLoad()
1006 DstVT = MVT::i32; in SelectIndexedLoad()
1010 if (DstVT == MVT::i64) in SelectIndexedLoad()
1016 InsertTo64 = DstVT == MVT::i64; in SelectIndexedLoad()
1019 DstVT = MVT::i32; in SelectIndexedLoad()
1035 SDNode *Res = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, DstVT, in SelectIndexedLoad()
/external/llvm/lib/CodeGen/
DCodeGenPrepare.cpp723 EVT DstVT = TLI.getValueType(CI->getType()); in OptimizeNoopCopyExpression() local
726 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
731 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
739 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
741 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
744 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1554 MVT DstVT; in SelectIToFP() local
1556 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1587 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1598 MVT DstVT; in SelectFPToI() local
1600 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1619 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
DARMISelLowering.cpp4018 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local
4019 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && in ExpandBITCAST()
4023 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { in ExpandBITCAST()
4028 return DAG.getNode(ISD::BITCAST, dl, DstVT, in ExpandBITCAST()
4033 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { in ExpandBITCAST()