| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 498 FLOG, FLOG2, FLOG10, FEXP, FEXP2, enumerator
|
| D | BasicTTIImpl.h | 572 ISD = ISD::FEXP2; in getIntrinsicInstrCost()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 159 case ISD::FEXP2: return "fexp2"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 79 case ISD::FEXP2: R = SoftenFloatRes_FEXP2(N); break; in SoftenFloatResult()
895 case ISD::FEXP2: ExpandFloatRes_FEXP2(N, Lo, Hi); break; in ExpandFloatResult()
1738 case ISD::FEXP2: in PromoteFloatResult()
|
| D | LegalizeVectorOps.cpp | 310 case ISD::FEXP2: in LegalizeOp()
|
| D | LegalizeVectorTypes.cpp | 80 case ISD::FEXP2: in ScalarizeVectorResult()
621 case ISD::FEXP2: in SplitVectorResult()
1803 case ISD::FEXP2: in WidenVectorResult()
|
| D | LegalizeDAG.cpp | 3348 case ISD::FEXP2: in ExpandNode()
4256 case ISD::FEXP2: { in PromoteNode()
|
| D | SelectionDAGBuilder.cpp | 4348 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op); in expandExp2()
6060 if (visitUnaryFloatCall(I, ISD::FEXP2)) in visitCall()
|
| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 122 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
367 setOperationAction(ISD::FEXP2, VT, Expand); in AMDGPUTargetLowering()
1031 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 837 setOperationAction(ISD::FEXP2, VT, Expand); in initActions()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 313 setOperationAction(ISD::FEXP2, Ty, Legal); in addMSAFloatType()
1852 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); in lowerINTRINSIC_WO_CHAIN()
|
| D | MipsMSAInstrInfo.td | 2082 // 1.0 when we only need to match ISD::FEXP2.
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 405 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 309 setOperationAction(ISD::FEXP2, MVT::f16, Promote); in AArch64TargetLowering()
358 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand); in AArch64TargetLowering()
392 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand); in AArch64TargetLowering()
646 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand); in addTypeForNEON()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 473 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); in ARMTargetLowering()
491 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); in ARMTargetLowering()
508 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand); in ARMTargetLowering()
612 setOperationAction(ISD::FEXP2, MVT::f64, Expand); in ARMTargetLowering()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 450 setOperationAction(ISD::FEXP2, VT, Expand); in PPCTargetLowering()
671 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand); in PPCTargetLowering()
717 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand); in PPCTargetLowering()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 661 setOperationAction(ISD::FEXP2, MVT::f80, Expand); in X86TargetLowering()
725 setOperationAction(ISD::FEXP2, VT, Expand); in X86TargetLowering()
|