| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 255 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
264 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
269 unsigned getIndexReg() { return IndexReg; } in getIndexReg()
362 assert (!IndexReg && "BaseReg/IndexReg already set!"); in onPlus()
363 IndexReg = TmpReg; in onPlus()
399 assert (!IndexReg && "BaseReg/IndexReg already set!"); in onMinus()
400 IndexReg = TmpReg; in onMinus()
436 assert (!IndexReg && "IndexReg already set!"); in onRegister()
438 IndexReg = Reg; in onRegister()
485 assert (!IndexReg && "IndexReg already set!"); in onInteger()
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| D | X86Operand.h | 53 unsigned IndexReg; member
118 return Mem.IndexReg; in getMemIndexReg()
484 Res->Mem.IndexReg = 0;
497 unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
502 assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
511 Res->Mem.IndexReg = IndexReg;
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 49 unsigned IndexReg; member
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr), in X86AddressMode()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
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| D | X86ISelDAGToDAG.cpp | 63 SDValue IndexReg; member
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), in X86ISelAddressMode()
87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
116 if (IndexReg.getNode()) in dump()
117 IndexReg.getNode()->dump(); in dump()
244 Index = AM.IndexReg; in getAddressOperands()
751 AM.Base_Reg = AM.IndexReg; in MatchAddress()
763 AM.IndexReg.getNode() == nullptr && in MatchAddress()
823 AM.IndexReg = And; in FoldMaskAndShiftToExtract()
867 AM.IndexReg = NewAnd; in FoldMaskedShiftToScaledMask()
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| D | X86AsmPrinter.cpp | 239 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printLeaMemReference() local
249 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
269 assert(IndexReg.getReg() != X86::ESP && in printLeaMemReference()
276 if (IndexReg.getReg()) { in printLeaMemReference()
305 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printIntelMemReference() local
323 if (IndexReg.getReg()) { in printIntelMemReference()
336 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printIntelMemReference()
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| D | X86MCInstLower.cpp | 762 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in EmitNops() local
763 Opc = IndexReg = Displacement = SegmentReg = 0; in EmitNops()
772 IndexReg = X86::RAX; break; in EmitNops()
774 IndexReg = X86::RAX; break; in EmitNops()
777 IndexReg = X86::RAX; break; in EmitNops()
779 IndexReg = X86::RAX; break; in EmitNops()
781 IndexReg = X86::RAX; SegmentReg = X86::CS; break; in EmitNops()
800 .addImm(ScaleVal).addReg(IndexReg) in EmitNops()
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| D | X86FastISel.cpp | 549 (AM.Base.Reg == 0 && AM.IndexReg == 0)) { in handleConstantAddresses()
568 assert(AM.Base.Reg == 0 && AM.IndexReg == 0); in handleConstantAddresses()
630 if (AM.IndexReg == 0) { in handleConstantAddresses()
632 AM.IndexReg = getRegForValue(V); in handleConstantAddresses()
633 return AM.IndexReg != 0; in handleConstantAddresses()
716 unsigned IndexReg = AM.IndexReg; in X86SelectAddress() local
748 if (IndexReg == 0 && in X86SelectAddress()
753 IndexReg = getRegForGEPIndex(Op).first; in X86SelectAddress()
754 if (IndexReg == 0) in X86SelectAddress()
767 AM.IndexReg = IndexReg; in X86SelectAddress()
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| D | X86ISelLowering.cpp | 19202 AM.IndexReg = Op.getImm(); in EmitInstrWithCustomInserter()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is16BitMemOperand() local
69 (IndexReg.getReg() != 0 && in Is16BitMemOperand()
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) in Is16BitMemOperand()
227 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is32BitMemOperand() local
231 (IndexReg.getReg() != 0 && in Is32BitMemOperand()
232 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) in Is32BitMemOperand()
242 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is64BitMemOperand() local
246 (IndexReg.getReg() != 0 && in Is64BitMemOperand()
247 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) in Is64BitMemOperand()
371 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in EmitMemModRMByte() local
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 188 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
202 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) in printMemReference()
209 if (IndexReg.getReg() || BaseReg.getReg()) { in printMemReference()
214 if (IndexReg.getReg()) { in printMemReference()
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| D | X86IntelInstPrinter.cpp | 161 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
179 if (IndexReg.getReg()) { in printMemReference()
193 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) { in printMemReference()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 158 unsigned &IndexReg);
402 unsigned &IndexReg) { in PPCSimplifyAddress() argument
424 IndexReg = PPCMaterializeInt(Offset, MVT::i64); in PPCSimplifyAddress()
425 assert(IndexReg && "Unexpected error in PPCMaterializeInt!"); in PPCSimplifyAddress()
489 unsigned IndexReg = 0; in PPCEmitLoad() local
490 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg); in PPCEmitLoad()
550 .addReg(Addr.Base.Reg).addReg(IndexReg); in PPCEmitLoad()
622 unsigned IndexReg = 0; in PPCEmitStore() local
623 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg); in PPCEmitStore()
686 if (IndexReg) in PPCEmitStore()
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| /external/llvm/lib/Target/R600/ |
| D | SIInstrInfo.h | 329 unsigned SavReg, unsigned IndexReg) const;
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 2971 unsigned IndexReg = MI->getOperand(3).getReg(); in emitCondStore() local
2981 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) { in emitCondStore()
3013 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg); in emitCondStore()
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| /external/llvm/docs/ |
| D | CodeGenerator.rst | 2165 SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
2174 Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
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