| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 61 int MCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
65 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
67 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
72 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum() argument
76 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
78 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); in getLLVMRegNum()
82 int MCRegisterInfo::getSEHRegNum(unsigned RegNum) const { in getSEHRegNum()
83 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
84 if (I == L2SEHRegs.end()) return (int)RegNum; in getSEHRegNum()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 173 unsigned RegNum; member
178 unsigned RegNum; member
361 return Reg.RegNum; in getReg()
366 return VectorList.RegNum; in getVectorListStart()
871 Reg.RegNum); in isVectorRegLo()
875 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum); in isGPR32as64()
880 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum); in isGPR64sp0()
1542 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateReg() argument
1544 Op->Reg.RegNum = RegNum; in CreateReg()
1552 CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements, in CreateVectorList() argument
[all …]
|
| /external/llvm/test/CodeGen/X86/ |
| D | stackmap-large-constants.ll | 40 ; Dwarf RegNum
70 ; Dwarf RegNum
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 158 unsigned RegNum; member
205 return Reg.RegNum; in getReg()
299 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, in CreateReg() argument
302 Op->Reg.RegNum = RegNum; in CreateReg()
324 Op.Reg.RegNum = DoubleRegs[regIdx / 2]; in MorphToDoubleReg()
347 Op.Reg.RegNum = Reg; in MorphToQuadReg()
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 390 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
393 int getLLVMRegNum(unsigned RegNum, bool isEH) const;
397 int getSEHRegNum(unsigned RegNum) const;
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 465 unsigned RegNum; member
470 unsigned RegNum; member
499 unsigned RegNum; member
677 return Reg.RegNum; in getReg()
1444 .contains(VectorList.RegNum)); in isVecListDPair()
1461 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
1488 .contains(VectorList.RegNum)); in isVecListDPairAllLanes()
1763 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands() local
1764 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
2186 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); in addAM3OffsetOperands()
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 266 unsigned RegNum = TRI->getEncodingValue(Reg); in printSavedRegsBitmask() local
271 FPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
274 FPUBitmask |= (3 << RegNum); in printSavedRegsBitmask()
278 CPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
|
| /external/clang/lib/Basic/ |
| D | TargetInfo.cpp | 369 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in isValidGCCRegisterName()
422 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in getNormalizedGCCRegisterName()
|
| /external/llvm/lib/Target/R600/ |
| D | AMDILCFGStructurizer.cpp | 239 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
241 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
518 MachineBasicBlock::iterator I, int NewOpcode, int RegNum, in insertCondBranchBefore() argument
524 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); in insertCondBranchBefore()
529 int NewOpcode, int RegNum) { in insertCondBranchEnd() argument
534 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false); in insertCondBranchEnd()
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 1465 unsigned RegNum = GetX86RegNum(MO) << 4; in EncodeInstruction() local
1467 RegNum |= 1 << 7; in EncodeInstruction()
1475 RegNum |= Val; in EncodeInstruction()
1478 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, in EncodeInstruction()
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 1760 unsigned RegNum; in DecodeRegListOperand() local
1767 RegNum = RegLst & 0xf; in DecodeRegListOperand()
1768 for (unsigned i = 0; i < RegNum; i++) in DecodeRegListOperand()
1782 unsigned RegNum = RegLst & 0x3; in DecodeRegListOperand16() local
1784 for (unsigned i = 0; i <= RegNum; i++) in DecodeRegListOperand16()
|
| /external/clang/include/clang/Basic/ |
| D | TargetInfo.h | 668 const unsigned RegNum; member
|
| /external/llvm/docs/ |
| D | StackMaps.rst | 346 uint16 : Dwarf RegNum
352 uint16 : Dwarf RegNum
360 interpret the ``RegNum`` and ``Offset`` fields as follows:
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILCFGStructurizer.cpp | 382 void addLoopBreakOnReg(LoopT *LoopRep, RegiT RegNum);
383 void addLoopContOnReg(LoopT *LoopRep, RegiT RegNum);
384 void addLoopBreakInitReg(LoopT *LoopRep, RegiT RegNum);
385 void addLoopContInitReg(LoopT *LoopRep, RegiT RegNum);
386 void addLoopEndbranchInitReg(LoopT *LoopRep, RegiT RegNum);
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 870 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg); in MergeLDR_STR() local
876 ((isNotVFP && RegNum > PRegNum) || in MergeLDR_STR()
877 ((Count < Limit) && RegNum == PRegNum+1)) && in MergeLDR_STR()
882 PRegNum = RegNum; in MergeLDR_STR()
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 1343 unsigned RegNum = Reg.EnumValue; in computeUberSets() local
1344 if (AllocatableRegs.count(RegNum)) in computeUberSets()
1347 UberSetIDs.join(0, RegNum); in computeUberSets()
|
| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 947 auto GetRegisterName = [](unsigned RegNum) -> StringRef { in getShuffleComment() argument
948 return X86ATTInstPrinter::getRegisterName(RegNum); in getShuffleComment()
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 1120 if (unsigned RegNum = MO2.getReg()) { in printThumbAddrModeRROperand() local
1122 printRegName(O, RegNum); in printThumbAddrModeRROperand()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXAsmPrinter.cpp | 303 unsigned RegNum = RegMap[Reg]; in encodeVirtualRegister() local
325 Ret |= (RegNum & 0x0FFFFFFF); in encodeVirtualRegister()
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 260 int matchRegisterByNumber(unsigned RegNum, unsigned RegClass);
2409 int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { in matchRegisterByNumber() argument
2410 if (RegNum > in matchRegisterByNumber()
2414 return getReg(RegClass, RegNum); in matchRegisterByNumber()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 2395 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs() local
2401 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC32_SVR4_Custom_AlignArgRegs()
2402 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
2423 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
2427 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
2428 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
|