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Searched refs:RegState (Results 1 – 25 of 62) sorted by relevance

123

/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h29 namespace RegState {
73 flags & RegState::Define,
74 flags & RegState::Implicit,
75 flags & RegState::Kill,
76 flags & RegState::Dead,
77 flags & RegState::Undef,
78 flags & RegState::EarlyClobber,
80 flags & RegState::Debug,
81 flags & RegState::InternalRead));
249 .addReg(DestReg, RegState::Define); in BuildMI()
[all …]
/external/llvm/lib/Target/R600/
DSIPrepareScratchRegs.cpp103 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in runOnMachineFunction()
104 .addReg(AMDGPU::SGPR0, RegState::Undef); in runOnMachineFunction()
159 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
163 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
167 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
171 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
179 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in runOnMachineFunction()
180 .addReg(AMDGPU::SGPR0, RegState::Undef); in runOnMachineFunction()
DSILowerControlFlow.cpp402 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectSrc()
403 .addReg(Vec, RegState::Implicit); in IndirectSrc()
422 .addReg(SubReg + Off, RegState::Define) in IndirectDst()
424 .addReg(AMDGPU::M0, RegState::Implicit) in IndirectDst()
425 .addReg(Dst, RegState::Implicit); in IndirectDst()
DR600InstrInfo.cpp71 RegState::Define | RegState::Implicit); in copyPhysReg()
801 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in InsertBranch()
816 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in InsertBranch()
1029 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1037 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
1138 RegState::Implicit | RegState::Kill); in buildIndirectWrite()
1171 RegState::Implicit | RegState::Kill); in buildIndirectRead()
DSIInstrInfo.cpp425 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
504 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in storeRegToStackSlot()
505 .addReg(AMDGPU::SGPR0, RegState::Undef); in storeRegToStackSlot()
551 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in loadRegFromStackSlot()
552 .addReg(AMDGPU::SGPR0, RegState::Undef); in loadRegFromStackSlot()
688 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit); in expandPostRAPseudo()
692 .addReg(AMDGPU::SCC, RegState::Define | RegState::Implicit) in expandPostRAPseudo()
693 .addReg(AMDGPU::SCC, RegState::Implicit); in expandPostRAPseudo()
714 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
717 .addReg(Dst, RegState::Implicit); in expandPostRAPseudo()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp109 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
116 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
122 .addReg(ScratchOffset, RegState::Kill); in InsertFPConstInst()
185 .addReg(ScratchBase, RegState::Kill) in InsertSPConstInst()
186 .addReg(ScratchOffset, RegState::Kill) in InsertSPConstInst()
192 .addReg(ScratchBase, RegState::Kill) in InsertSPConstInst()
193 .addReg(ScratchOffset, RegState::Kill) in InsertSPConstInst()
198 .addReg(ScratchBase, RegState::Kill) in InsertSPConstInst()
199 .addReg(ScratchOffset, RegState::Kill); in InsertSPConstInst()
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp389 .addReg(NegSizeReg1, RegState::Kill); in lowerDynamicAlloc()
394 .addReg(Reg, RegState::Kill) in lowerDynamicAlloc()
414 .addReg(NegSizeReg1, RegState::Kill); in lowerDynamicAlloc()
419 .addReg(Reg, RegState::Kill) in lowerDynamicAlloc()
470 .addReg(Reg1, RegState::Kill) in lowerCRSpilling()
477 .addReg(Reg, RegState::Kill), in lowerCRSpilling()
516 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
521 .addReg(Reg, RegState::Kill); in lowerCRRestore()
559 .addReg(Reg1, RegState::Kill) in lowerCRBitSpilling()
564 .addReg(Reg, RegState::Kill), in lowerCRBitSpilling()
[all …]
DPPCFrameLowering.cpp357 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
366 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
375 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
379 .addReg(DstReg, RegState::Kill) in HandleVRSaveUpdate()
701 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); in emitPrologue()
765 .addReg(ScratchReg, RegState::Kill) in emitPrologue()
771 .addReg(TempReg, RegState::Kill) in emitPrologue()
774 .addReg(ScratchReg, RegState::Kill) in emitPrologue()
775 .addReg(TempReg, RegState::Kill); in emitPrologue()
778 .addReg(SPReg, RegState::Kill) in emitPrologue()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DR600InstrInfo.cpp59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) in copyPhysReg()
63 .addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); in getMovImmInstr()
281 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in InsertBranch()
291 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in InsertBranch()
463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()
DR600ISelLowering.cpp173 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
174 .addReg(t1, RegState::Implicit); in EmitInstrWithCustomInserter()
195 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
196 .addReg(t1, RegState::Implicit); in EmitInstrWithCustomInserter()
215 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in EmitInstrWithCustomInserter()
229 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in EmitInstrWithCustomInserter()
DSIInstrInfo.cpp56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); in getMovImmInstr()
/external/llvm/lib/Target/ARM/
DThumb1FrameLowering.cpp419 .addReg(ARM::R3, RegState::Define); in emitEpilogue()
425 .addReg(ARM::R3, RegState::Kill); in emitEpilogue()
432 .addReg(ARM::R12, RegState::Define) in emitEpilogue()
433 .addReg(ARM::R3, RegState::Kill)); in emitEpilogue()
436 .addReg(ARM::R3, RegState::Define); in emitEpilogue()
441 .addReg(ARM::LR, RegState::Define) in emitEpilogue()
442 .addReg(ARM::R3, RegState::Kill)); in emitEpilogue()
445 .addReg(ARM::R3, RegState::Define) in emitEpilogue()
446 .addReg(ARM::R12, RegState::Kill)); in emitEpilogue()
DARMExpandPseudoInsts.cpp397 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
399 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
401 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
403 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
434 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
487 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. in ExpandVST()
530 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
532 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
534 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
536 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandLaneOp()
[all …]
DARMFrameLowering.cpp250 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
255 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
264 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
268 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
276 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
456 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
467 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
468 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
475 .addReg(ARM::SP, RegState::Define) in emitPrologue()
476 .addReg(ARM::R4, RegState::Kill) in emitPrologue()
[all …]
DARMBaseInstrInfo.cpp712 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
734 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
1109 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1110 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1119 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1120 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1124 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1153 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1154 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1155 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
[all …]
DThumb2InstrInfo.cpp198 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
199 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
204 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
227 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
259 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
260 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
265 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
266 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
331 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
DThumbRegisterInfo.cpp157 .addReg(LdReg, RegState::Kill).setMIFlags(MIFlags); in emitThumbRegPlusImmInReg()
170 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
172 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
309 MIB.addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmediate()
462 .addReg(ARM::R12, RegState::Define) in saveScavengerRegister()
463 .addReg(Reg, RegState::Kill)); in saveScavengerRegister()
492 addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill)); in saveScavengerRegister()
DARMFastISel.cpp297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
300 .addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
323 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
324 .addReg(Op1, Op1IsKill * RegState::Kill)); in fastEmitInst_rr()
327 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
328 .addReg(Op1, Op1IsKill * RegState::Kill)); in fastEmitInst_rr()
353 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rrr()
354 .addReg(Op1, Op1IsKill * RegState::Kill) in fastEmitInst_rrr()
355 .addReg(Op2, Op2IsKill * RegState::Kill)); in fastEmitInst_rrr()
358 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rrr()
[all …]
/external/llvm/lib/Target/Mips/
DMips16InstrInfo.cpp87 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
251 addSaveRestoreRegs(MIB, CSI, RegState::Define); in restoreFrame()
253 MIB.addReg(Mips::S2, RegState::Define); in restoreFrame()
277 MIB2.addReg(Mips::SP, RegState::Kill); in adjustStackPtrBig()
280 MIB3.addReg(Reg2, RegState::Kill); in adjustStackPtrBig()
283 MIB4.addReg(Reg1, RegState::Kill); in adjustStackPtrBig()
403 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill) in loadImmediate()
408 .addReg(Reg, RegState::Kill); in loadImmediate()
DMipsSEInstrInfo.cpp108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
130 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
170 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
374 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); in adjustStackPtr()
413 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) in loadImmediate()
483 LoInst.addReg(DstLo, RegState::Define); in expandPseudoMTLoHi()
484 HiInst.addReg(DstHi, RegState::Define); in expandPseudoMTLoHi()
509 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()
DMipsSEFrameLowering.cpp161 .addReg(VR, RegState::Kill); in expandLoadCCond()
198 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); in expandLoadACC()
200 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
255 .addReg(VR0, RegState::Kill); in expandCopyACC()
258 .addReg(VR1, RegState::Kill); in expandCopyACC()
/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp110 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryOrrMovk()
188 RegState::Define | getDeadRegState(DstIsDead && CountThree)) in tryToreplicateChunks()
212 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryToreplicateChunks()
362 RegState::Define | getDeadRegState(DstIsDead && SingleMovk)) in trySequenceOfOnes()
378 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in trySequenceOfOnes()
527 .addReg(DstReg, RegState::Define | in expandMOVImm()
552 RegState::Define | in expandMOVImm()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp240 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
253 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
265 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
706 MIB.addReg(0U, RegState::Debug); in EmitDbgValue()
802 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
803 RegState::EarlyClobber); in EmitMachineNode()
974 MIB.addReg(Reg, RegState::Define | in EmitSpecialNode()
982 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber | in EmitSpecialNode()
/external/llvm/lib/Target/X86/
DX86FrameLowering.cpp439 CI.addReg(AX, RegState::Implicit) in emitStackProbeCall()
440 .addReg(SP, RegState::Implicit) in emitStackProbeCall()
441 .addReg(AX, RegState::Define | RegState::Implicit) in emitStackProbeCall()
442 .addReg(SP, RegState::Define | RegState::Implicit) in emitStackProbeCall()
443 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); in emitStackProbeCall()
689 .addReg(MachineFramePtr, RegState::Kill) in emitPrologue()
816 .addReg(X86::EAX, RegState::Kill) in emitPrologue()
1175 .addReg(JumpTarget.getReg(), RegState::Kill); in emitEpilogue()
1178 addReg(JumpTarget.getReg(), RegState::Kill); in emitEpilogue()
1450 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill) in spillCalleeSavedRegisters()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp207 .addReg(SystemZ::CC, RegState::ImplicitDefine); in convertToBRCT()
221 .addReg(SystemZ::CC, RegState::ImplicitDefine); in convertToLoadAndTest()
411 .addReg(SystemZ::CC, RegState::ImplicitDefine); in fuseCompareAndBranch()

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