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Searched refs:RegVT (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/CodeGen/
DCallingConvLower.cpp239 for (MVT RegVT : RegParmTypes) { in analyzeMustTailForwardedRegisters() local
241 getRemainingRegParmsForType(RemainingRegs, RegVT, Fn); in analyzeMustTailForwardedRegisters()
243 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
246 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT)); in analyzeMustTailForwardedRegisters()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp213 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
214 switch (RegVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
217 << RegVT.getSimpleVT().SimpleTy << '\n'; in LowerFormalArguments()
223 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerFormalArguments()
229 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
232 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp457 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
458 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
463 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
470 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
476 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerCCCArguments()
479 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp1915 B.RegVT = VT.getSimpleVT(); in visitBitTestHeader()
1916 B.Reg = FuncInfo.CreateReg(B.RegVT); in visitBitTestHeader()
1944 MVT VT = BB.RegVT; in visitBitTestCase()
6213 MVT RegVT = *PhysReg.second->vt_begin(); in GetRegistersForValue() local
6214 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) { in GetRegistersForValue()
6216 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
6217 OpInfo.ConstraintVT = RegVT; in GetRegistersForValue()
6218 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { in GetRegistersForValue()
6223 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); in GetRegistersForValue()
6225 RegVT, OpInfo.CallOperand); in GetRegistersForValue()
[all …]
DSelectionDAGBuilder.h278 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E), in BitTestBlock()
284 MVT RegVT; member
DLegalizeDAG.cpp319 MVT RegVT = in ExpandUnalignedStore() local
324 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedStore()
328 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); in ExpandUnalignedStore()
341 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, in ExpandUnalignedStore()
363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
443 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); in ExpandUnalignedLoad() local
445 unsigned RegBytes = RegVT.getSizeInBits() / 8; in ExpandUnalignedLoad()
449 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in ExpandUnalignedLoad()
459 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, in ExpandUnalignedLoad()
478 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, in ExpandUnalignedLoad()
DLegalizeVectorOps.cpp639 EVT RegVT = Value.getValueType(); in ExpandStore() local
640 EVT RegSclVT = RegVT.getScalarType(); in ExpandStore()
DLegalizeIntegerTypes.cpp775 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT); in PromoteIntRes_VAARG() local
781 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2), in PromoteIntRes_VAARG()
797 DAG.getConstant(i * RegVT.getSizeInBits(), in PromoteIntRes_VAARG()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp882 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
883 if (RegVT == MVT::i8 || RegVT == MVT::i16 || in LowerFormalArguments()
884 RegVT == MVT::i32 || RegVT == MVT::f32) { in LowerFormalArguments()
888 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
889 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) { in LowerFormalArguments()
893 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); in LowerFormalArguments()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp2950 MVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
2952 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
2957 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
2963 if ((RegVT == MVT::i32 && ValVT == MVT::f32) || in LowerFormalArguments()
2964 (RegVT == MVT::i64 && ValVT == MVT::f64) || in LowerFormalArguments()
2965 (RegVT == MVT::f64 && ValVT == MVT::i64)) in LowerFormalArguments()
2967 else if (ABI.IsO32() && RegVT == MVT::i32 && in LowerFormalArguments()
2971 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); in LowerFormalArguments()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1326 EVT RegVT = VA.getLocVT(); in LowerCCCArguments() local
1327 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCCCArguments()
1332 << RegVT.getSimpleVT().SimpleTy << "\n"; in LowerCCCArguments()
1339 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); in LowerCCCArguments()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp2324 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
2326 if (RegVT == MVT::i32) in LowerFormalArguments()
2328 else if (Is64Bit && RegVT == MVT::i64) in LowerFormalArguments()
2330 else if (RegVT == MVT::f32) in LowerFormalArguments()
2332 else if (RegVT == MVT::f64) in LowerFormalArguments()
2334 else if (RegVT.is512BitVector()) in LowerFormalArguments()
2336 else if (RegVT.is256BitVector()) in LowerFormalArguments()
2338 else if (RegVT.is128BitVector()) in LowerFormalArguments()
2340 else if (RegVT == MVT::x86mmx) in LowerFormalArguments()
2342 else if (RegVT == MVT::i1) in LowerFormalArguments()
[all …]
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp1293 EVT RegVT = getEquivalentLoadRegType(*DAG.getContext(), SrcVT); in performUCharToFloatCombine() local
1310 SDValue NewLoad = DAG.getExtLoad(ISD::ZEXTLOAD, DL, RegVT, in performUCharToFloatCombine()
1321 if (RegVT.isVector()) in performUCharToFloatCombine()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp2117 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
2122 if (RegVT == MVT::i32) in LowerFormalArguments()
2124 else if (RegVT == MVT::i64) in LowerFormalArguments()
2126 else if (RegVT == MVT::f16) in LowerFormalArguments()
2128 else if (RegVT == MVT::f32) in LowerFormalArguments()
2130 else if (RegVT == MVT::f64 || RegVT.is64BitVector()) in LowerFormalArguments()
2132 else if (RegVT == MVT::f128 || RegVT.is128BitVector()) in LowerFormalArguments()
2139 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
2157 assert(RegVT == Ins[i].VT && "incorrect register location selected"); in LowerFormalArguments()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp2098 EVT RegVT = VA.getLocVT(); in IsEligibleForTailCallOptimization() local
2112 if (RegVT == MVT::v2f64) { in IsEligibleForTailCallOptimization()
2991 EVT RegVT = VA.getLocVT(); in LowerFormalArguments() local
3022 if (RegVT == MVT::f32) in LowerFormalArguments()
3024 else if (RegVT == MVT::f64) in LowerFormalArguments()
3026 else if (RegVT == MVT::v2f64) in LowerFormalArguments()
3028 else if (RegVT == MVT::i32) in LowerFormalArguments()
3036 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); in LowerFormalArguments()
3049 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, in LowerFormalArguments()
3054 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()