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Searched refs:Regs (Results 1 – 25 of 33) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h318 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const { in getFirstUnallocated() argument
319 for (unsigned i = 0; i < Regs.size(); ++i) in getFirstUnallocated()
320 if (!isAllocated(Regs[i])) in getFirstUnallocated()
322 return Regs.size(); in getFirstUnallocated()
345 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) { in AllocateReg() argument
346 unsigned FirstUnalloc = getFirstUnallocated(Regs); in AllocateReg()
347 if (FirstUnalloc == Regs.size()) in AllocateReg()
351 unsigned Reg = Regs[FirstUnalloc]; in AllocateReg()
359 unsigned AllocateRegBlock(ArrayRef<uint16_t> Regs, unsigned RegsRequired) { in AllocateRegBlock() argument
360 if (RegsRequired > Regs.size()) in AllocateRegBlock()
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DRegisterPressure.h290 void addLiveRegs(ArrayRef<unsigned> Regs);
415 void increaseRegPressure(ArrayRef<unsigned> Regs);
416 void decreaseRegPressure(ArrayRef<unsigned> Regs);
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp50 const unsigned *Regs) { in decodeRegisterClass() argument
52 RegNo = Regs[RegNo]; in decodeRegisterClass()
188 const unsigned *Regs) { in decodeBDAddr12Operand() argument
192 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
198 const unsigned *Regs) { in decodeBDAddr20Operand() argument
202 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
208 const unsigned *Regs) { in decodeBDXAddr12Operand() argument
213 Inst.addOperand(MCOperand::CreateReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
215 Inst.addOperand(MCOperand::CreateReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
220 const unsigned *Regs) { in decodeBDXAddr20Operand() argument
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/external/llvm/utils/TableGen/
DRegisterInfoEmitter.cpp56 void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
59 const std::deque<CodeGenRegister> &Regs,
183 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure() local
184 if (Regs.empty()) in EmitRegUnitPressure()
189 OS << " {" << (*Regs.begin())->getWeight(RegBank) in EmitRegUnitPressure()
321 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
328 for (auto &RE : Regs) { in EmitRegMappingTables()
347 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace"); in EmitRegMappingTables()
395 for (auto &RE : Regs) { in EmitRegMappingTables()
444 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
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DCodeGenRegisters.cpp160 RegUnitIterator(const CodeGenRegister::Vec &Regs): in RegUnitIterator() argument
161 RegI(Regs.begin()), RegE(Regs.end()), UnitI(), UnitE() { in RegUnitIterator()
940 std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); in CodeGenRegBank() local
941 std::sort(Regs.begin(), Regs.end(), LessRecordRegister()); in CodeGenRegBank()
943 for (unsigned i = 0, e = Regs.size(); i != e; ++i) in CodeGenRegBank()
944 getReg(Regs[i]); in CodeGenRegBank()
1299 CodeGenRegister::Vec Regs; member
1328 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets() local
1329 if (Regs.empty()) in computeUberSets()
1332 unsigned USetID = UberSetIDs.findLeader((*Regs.begin())->EnumValue); in computeUberSets()
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DCodeGenTarget.cpp224 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); in getRegisterByName() local
225 StringMap<CodeGenRegister*>::const_iterator I = Regs.find(Name); in getRegisterByName()
226 if (I == Regs.end()) in getRegisterByName()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMUnwindOpAsm.cpp106 for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) { in EmitVFPRegSave()
107 while (Regs) { in EmitVFPRegSave()
109 auto RangeMSB = 32 - countLeadingZeros(Regs); in EmitVFPRegSave()
110 auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB)); in EmitVFPRegSave()
120 Regs &= ~(-1u << RangeLSB); in EmitVFPRegSave()
/external/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp342 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
346 RegisterGroup Group, const unsigned *Regs,
351 const unsigned *Regs, RegisterKind RegKind);
354 const unsigned *Regs, RegisterKind RegKind,
497 const unsigned *Regs, bool IsAddress) { in parseRegister() argument
502 if (Regs && Regs[Reg.Num] == 0) in parseRegister()
506 if (Regs) in parseRegister()
507 Reg.Num = Regs[Reg.Num]; in parseRegister()
514 const unsigned *Regs, RegisterKind Kind) { in parseRegister() argument
520 if (parseRegister(Reg, Group, Regs, IsAddress)) in parseRegister()
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/external/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp70 std::vector<unsigned> &Regs, in GetGroupRegs() argument
75 Regs.push_back(Reg); in GetGroupRegs()
549 std::vector<unsigned> Regs; in FindSuitableFreeRegisters() local
550 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs); in FindSuitableFreeRegisters()
551 assert(Regs.size() > 0 && "Empty register group!"); in FindSuitableFreeRegisters()
552 if (Regs.size() == 0) in FindSuitableFreeRegisters()
562 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
563 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
582 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in FindSuitableFreeRegisters()
583 unsigned Reg = Regs[i]; in FindSuitableFreeRegisters()
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DExecutionDepsFix.cpp650 SmallVector<LiveReg, 4> Regs; in visitSoftInstr() local
662 for (SmallVectorImpl<LiveReg>::iterator i = Regs.begin(), e = Regs.end(); in visitSoftInstr()
666 Regs.insert(i, LR); in visitSoftInstr()
670 Regs.push_back(LR); in visitSoftInstr()
676 while (!Regs.empty()) { in visitSoftInstr()
678 dv = Regs.pop_back_val().Value; in visitSoftInstr()
685 DomainValue *Latest = Regs.pop_back_val().Value; in visitSoftInstr()
DCallingConvLower.cpp194 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, in getRemainingRegParmsForType() argument
222 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
DAggressiveAntiDepBreaker.h94 std::vector<unsigned> &Regs,
DRegisterPressure.cpp424 void RegPressureTracker::addLiveRegs(ArrayRef<unsigned> Regs) { in addLiveRegs() argument
425 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { in addLiveRegs()
426 if (LiveRegs.insert(Regs[i])) in addLiveRegs()
427 increaseRegPressure(Regs[i]); in addLiveRegs()
/external/llvm/lib/Target/ARM/
DARMFrameLowering.cpp946 SmallVector<std::pair<unsigned,bool>, 4> Regs; in emitPushInst() local
978 Regs.push_back(std::make_pair(Reg, isKill)); in emitPushInst()
981 if (Regs.empty()) in emitPushInst()
983 if (Regs.size() > 1 || StrOpc== 0) { in emitPushInst()
987 for (unsigned i = 0, e = Regs.size(); i < e; ++i) in emitPushInst()
988 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); in emitPushInst()
989 } else if (Regs.size() == 1) { in emitPushInst()
992 .addReg(Regs[0].first, getKillRegState(Regs[0].second)) in emitPushInst()
997 Regs.clear(); in emitPushInst()
1023 SmallVector<unsigned, 4> Regs; in emitPopInst() local
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DARMLoadStoreOptimizer.cpp109 ArrayRef<std::pair<unsigned, bool> > Regs,
483 ArrayRef<std::pair<unsigned, bool> > Regs, in MergeOps()
486 unsigned NumRegs = Regs.size(); in MergeOps()
503 if (Base == Regs[I].first) { in MergeOps()
545 NewBase = Regs[NumRegs-1].first; in MergeOps()
660 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) in MergeOps()
661 | getKillRegState(Regs[i].second)); in MergeOps()
756 SmallVector<std::pair<unsigned, bool>, 8> Regs; in MergeOpsUpdate() local
764 Regs.push_back(std::make_pair(Reg, isKill)); in MergeOpsUpdate()
786 Pred, PredReg, Scratch, dl, Regs, ImpDefs)) in MergeOpsUpdate()
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DThumb2SizeReduction.cpp215 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef() local
216 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp897 SDValue AArch64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) { in createDTuple() argument
903 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
906 SDValue AArch64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) { in createQTuple() argument
912 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
915 SDValue AArch64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs, in createTuple() argument
920 if (Regs.size() == 1) in createTuple()
921 return Regs[0]; in createTuple()
923 assert(Regs.size() >= 2 && Regs.size() <= 4); in createTuple()
925 SDLoc DL(Regs[0].getNode()); in createTuple()
931 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], MVT::i32)); in createTuple()
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/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV3.td24 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicable = 1,
39 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicated = 1,
67 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
80 let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
/external/llvm/lib/CodeGen/AsmPrinter/
DDbgValueHistoryCalculator.cpp171 BitVector &Regs) { in collectChangingRegs() argument
179 applyToClobberedRegisters(MI, TRI, [&](unsigned r) { Regs.set(r); }); in collectChangingRegs()
/external/llvm/lib/Transforms/Scalar/
DLoopStrengthReduce.cpp894 SmallPtrSetImpl<const SCEV *> &Regs,
907 SmallPtrSetImpl<const SCEV *> &Regs,
911 SmallPtrSetImpl<const SCEV *> &Regs,
921 SmallPtrSetImpl<const SCEV *> &Regs, in RateRegister() argument
943 if (!Regs.count(AR->getOperand(1))) { in RateRegister()
944 RateRegister(AR->getOperand(1), Regs, L, SE, DT); in RateRegister()
969 SmallPtrSetImpl<const SCEV *> &Regs, in RatePrimaryRegister() argument
977 if (Regs.insert(Reg).second) { in RatePrimaryRegister()
978 RateRegister(Reg, Regs, L, SE, DT); in RatePrimaryRegister()
986 SmallPtrSetImpl<const SCEV *> &Regs, in RateFormula() argument
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/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp611 SmallVector<unsigned, 4> Regs; member
617 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} in RegsForValue()
628 Regs.push_back(Reg + i); in RegsForValue()
638 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); in append()
697 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); in getCopyFromRegs()
699 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); in getCopyFromRegs()
708 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || in getCopyFromRegs()
713 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); in getCopyFromRegs()
778 unsigned NumRegs = Regs.size(); in getCopyToRegs()
798 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); in getCopyToRegs()
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/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp1080 CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc, in CreateRegList() argument
1082 assert (Regs.size() > 0 && "Empty list not allowed"); in CreateRegList()
1085 Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end()); in CreateRegList()
3011 SmallVector<unsigned, 10> Regs; in parseRegisterList() local
3029 Regs.push_back(RegNo); in parseRegisterList()
3039 Regs.push_back(TmpReg++); in parseRegisterList()
3059 Regs.push_back(RegNo); in parseRegisterList()
3079 Operands.push_back(MipsOperand::CreateRegList(Regs, S, E, *this)); in parseRegisterList()
3104 SmallVector<unsigned, 10> Regs; in parseMovePRegPair() local
3116 Regs.push_back(RegNo); in parseMovePRegPair()
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/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp180 const unsigned (&Regs)[N]) { in decodeRegisterClass()
182 Inst.addOperand(MCOperand::CreateReg(Regs[RegNo])); in decodeRegisterClass()
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp1758 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, in DecodeRegListOperand() local
1769 Inst.addOperand(MCOperand::CreateReg(Regs[i])); in DecodeRegListOperand()
1780 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; in DecodeRegListOperand16() local
1785 Inst.addOperand(MCOperand::CreateReg(Regs[i])); in DecodeRegListOperand16()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp564 SmallVector<SDValue, 4> Regs; in LowerFormalArguments() local
565 Regs.push_back(Val); in LowerFormalArguments()
569 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT)); in LowerFormalArguments()
574 Regs.append(NumElements, DAG.getUNDEF(VT)); in LowerFormalArguments()
576 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs)); in LowerFormalArguments()

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