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Searched refs:Rn (Results 1 – 25 of 50) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td586 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
587 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
588 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
589 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
590 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
591 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
592 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
593 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
594 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
595 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
[all …]
DAArch64InstrFormats.td966 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
967 bits<5> Rn;
968 let Inst{9-5} = Rn;
1130 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1131 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1175 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1176 [(set regtype:$Rd, (node regtype:$Rn))]>,
1179 bits<5> Rn;
1183 let Inst{9-5} = Rn;
1214 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
[all …]
DAArch64InstrAtomics.td45 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
47 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
48 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
50 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
51 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
53 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
55 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
56 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
60 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
62 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td279 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
285 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
310 bits<4> Rn;
322 bits<4> Rn;
325 let Inst{19-16} = Rn;
361 bits<4> Rn;
364 let Inst{19-16} = Rn;
394 bits<4> Rn;
397 let Inst{19-16} = Rn;
406 bits<4> Rn;
[all …]
DARMInstrInfo.td1213 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1220 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1221 iii, opc, "\t$Rd, $Rn, $imm",
1222 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1225 bits<4> Rn;
1228 let Inst{19-16} = Rn;
1233 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1234 iir, opc, "\t$Rd, $Rn, $Rm",
1235 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1238 bits<4> Rn;
[all …]
DARMInstrThumb.td372 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
383 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
404 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
405 "add", "\t$Rdn, $sp, $Rn", []>,
416 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
720 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
721 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
722 bits<3> Rn;
724 let Inst{10-8} = Rn;
733 "$Rn = $wb", IIC_iLoad_mu>,
[all …]
DARMInstrNEON.td616 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
618 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
623 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
625 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
673 (ins AddrMode:$Rn), IIC_VLD1,
674 "vld1", Dt, "$Vd, $Rn", "", []> {
676 let Inst{4} = Rn{4};
681 (ins AddrMode:$Rn), IIC_VLD1x2,
682 "vld1", Dt, "$Vd, $Rn", "", []> {
684 let Inst{5-4} = Rn{5-4};
[all …]
DARMSchedule.td18 // Rd <- ADD Rn, Rm, <shift> Rs
20 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
21 // | | uopc Rd, Rn, T0 - P01 - 1
24 // and one cycle after the result in Rn is available. The micro-ops can execute
27 // that the resource P01 is needed and that the latency to Rn is different than
28 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
DARMInstrFormats.td75 // The instruction has an Rn register operand.
77 // it doesn't have a Rn operand.
666 bits<4> Rn;
669 let Inst{19-16} = Rn;
684 bits<4> Rn;
687 let Inst{19-16} = Rn;
700 // {17-14} Rn
724 let Inst{19-16} = addr{12-9}; // Rn
754 // {12-9} Rn
764 let Inst{19-16} = addr; // Rn
[all …]
DARMInstrVFP.td124 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
126 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
132 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
135 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
141 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
144 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
152 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
154 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
164 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
167 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
[all …]
/external/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp1906 uint32_t Rn; // This function assumes Rn is the SP, but we should verify that. in EmulateSTRRtSP() local
1915 Rn = Bits32 (opcode, 19, 16); in EmulateSTRRtSP()
1917 if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP. in EmulateSTRRtSP()
1924 if (wback && ((Rn == 15) || (Rn == Rt))) in EmulateSTRRtSP()
2391 uint32_t Rn; // the base register which contains the address of the table of branch lengths in EmulateTB() local
2396 Rn = Bits32(opcode, 19, 16); in EmulateTB()
2399 if (Rn == 13 || BadReg(Rm)) in EmulateTB()
2530 uint64_t Rn = ReadRegisterUnsigned (eRegisterKindDWARF, dwarf_r0 + n, 0, &success); in EmulateADDImmThumb() local
2535 AddWithCarryResult res = AddWithCarry (Rn, imm32, 0); in EmulateADDImmThumb()
2582 uint32_t Rd, Rn; in EmulateADDImmARM() local
[all …]
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1333 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeCopMemInstruction() local
1383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeCopMemInstruction()
1479 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode2IdxInstruction() local
1498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1539 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1584 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeSORegMemOperand() local
1609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeSORegMemOperand()
1629 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode3Instruction() local
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/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt45 # Writeback is not allowed is Rn is in the target register list.
62 # if Rn = '1111' then SEE LDRD (literal)
159 # invalid STRi12 Rn=PC
164 # invalid STRi8 Rn=PC
169 # invalid STRs Rn=PC
174 # invalid STRBi12 Rn=PC
179 # invalid STRBi8 Rn=PC
184 # invalid STRBs Rn=PC
189 # invalid STRHi12 Rn=PC
194 # invalid STRHi8 Rn=PC
[all …]
/external/vixl/src/vixl/a64/
Dassembler-a64.cc624 Emit(BR | Rn(xn)); in br()
630 Emit(BLR | Rn(xn)); in blr()
636 Emit(RET | Rn(xn)); in ret()
701 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd)); in NEONTable()
1023 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1032 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1041 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1050 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1062 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in bfm()
1073 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in sbfm()
[all …]
Dsimulator-a64.cc860 const Instruction* target = Instruction::Cast(xreg(instr->Rn())); in VisitUnconditionalBranchToRegister()
916 reg(reg_size, instr->Rn(), instr->RnMode()), in AddSubHelper()
924 reg(reg_size, instr->Rn(), instr->RnMode()), in AddSubHelper()
973 reg(reg_size, instr->Rn()), in VisitAddSubWithCarry()
1001 int64_t op1 = reg(reg_size, instr->Rn()); in LogicalHelper()
1042 int64_t op1 = reg(reg_size, instr->Rn()); in ConditionalCompareHelper()
1098 uintptr_t address = AddressModeHelper(instr->Rn(), offset, addrmode); in LoadStoreHelper()
1196 uintptr_t address = AddressModeHelper(instr->Rn(), offset, addrmode); in LoadStorePairHelper()
1314 unsigned rn = instr->Rn(); in VisitLoadStoreExclusive()
1584 uint64_t new_val = xreg(instr->Rn()); in VisitConditionalSelect()
[all …]
Ddisasm-a64.h133 return (instr->Rn() == kZeroRegCode); in RnIsZROrSP()
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp645 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local
650 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
653 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
736 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local
764 DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
785 DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
831 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local
882 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); in DecodeUnsignedLdStInstruction()
892 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local
950 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); in DecodeSignedLdStInstruction()
[all …]
/external/v8/src/arm64/
Dassembler-arm64.cc899 instr->following()->Rn() == xzr.code())); in IsConstantPoolAt()
935 Emit(BLR | Rn(xzr)); in EmitPoolGuard()
956 Emit(BR | Rn(xn)); in br()
966 Emit(BLR | Rn(xn)); in blr()
973 Emit(RET | Rn(xn)); in ret()
1245 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1254 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1263 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1272 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1286 Rn(rn) | Rd(rd)); in bfm()
[all …]
Dsimulator-arm64.cc883 reg<T>(instr->Rn()), in AddSubWithCarry()
958 T op1 = reg<T>(instr->Rn()); in Extract()
1315 Instruction* target = reg<Instruction*>(instr->Rn()); in VisitUnconditionalBranchToRegister()
1319 if (instr->Rn() == 31) { in VisitUnconditionalBranchToRegister()
1374 reg<T>(instr->Rn(), instr->RnMode()), in AddSubHelper()
1381 reg<T>(instr->Rn(), instr->RnMode()), in AddSubHelper()
1466 T op1 = reg<T>(instr->Rn()); in LogicalHelper()
1513 T op1 = reg<T>(instr->Rn()); in ConditionalCompareHelper()
1567 unsigned addr_reg = instr->Rn(); in LoadStoreHelper()
1671 unsigned addr_reg = instr->Rn(); in LoadStorePairHelper()
[all …]
Ddisasm-arm64.h55 return (instr->Rn() == kZeroRegCode); in RnIsZROrSP()
/external/v8/src/arm/
Ddisasm-arm.cc91 void FormatNeonMemory(int Rn, int align, int Rm);
416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { in FormatNeonMemory() argument
418 "[r%d", Rn); in FormatNeonMemory()
1573 int Rn = instr->VnValue(); in DecodeSpecialCondition() local
1582 FormatNeonMemory(Rn, align, Rm); in DecodeSpecialCondition()
1586 int Rn = instr->VnValue(); in DecodeSpecialCondition() local
1595 FormatNeonMemory(Rn, align, Rm); in DecodeSpecialCondition()
1603 int Rn = instr->Bits(19, 16); in DecodeSpecialCondition() local
1607 "pld [r%d]", Rn); in DecodeSpecialCondition()
1610 "pld [r%d, #-%d]", Rn, offset); in DecodeSpecialCondition()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp873 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() local
875 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
1080 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getLdStSORegOpValue() local
1099 Binary |= Rn << 13; in getLdStSORegOpValue()
1116 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode2OpValue() local
1118 Binary |= Rn << 14; in getAddrMode2OpValue()
1192 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrMode3OpValue() local
1200 return (Rn << 9) | (1 << 13); in getAddrMode3OpValue()
1202 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode3OpValue() local
1210 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13); in getAddrMode3OpValue()
[all …]
/external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/es-ES/
Des-ES_kdt_g2p.pkb11 �U�����9���rEL_^���ZdM��e���8�X��4�չE%Mg�>�h�i�>K'`(�>~B`�Z�,�Rn
/external/llvm/test/CodeGen/AArch64/
Dzero-reg.ll23 ; instruction (0b11111 in the Rn field would mean "sp").
/external/vixl/examples/
Dnon-const-visitor.h41 int rn = instr->Rn(); in VisitAddSubShifted()

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