| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 155 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in BPFTargetLowering()
158 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in BPFTargetLowering()
159 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in BPFTargetLowering()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 758 SEXTLOAD, enumerator
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| D | SelectionDAGNodes.h | 2109 cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i16, Expand); in SITargetLowering()
152 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v16i16, Expand); in SITargetLowering()
391 return DAG.getLoad(ISD::UNINDEXED, Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD, in LowerParameter()
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| D | R600ISelLowering.cpp | 126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
127 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
1561 if (LoadNode->getExtensionType() == ISD::SEXTLOAD) { in LowerLOAD()
1693 Ext = ISD::SEXTLOAD; in LowerFormalArguments()
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| D | AMDGPUISelLowering.cpp | 223 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
232 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
235 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
238 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
1463 if (ExtType == ISD::SEXTLOAD) { in LowerLOAD()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 86 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
88 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 406 if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
592 LD->getExtensionType() != ISD::SEXTLOAD || in SelectMul()
618 LD->getExtensionType() != ISD::SEXTLOAD || in SelectMul()
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| D | HexagonOperands.td | 504 return LD->getExtensionType() == ISD::SEXTLOAD &&
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| D | HexagonISelLowering.cpp | 678 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; in getPostIndexedAddressParts()
1618 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 470 case ISD::SEXTLOAD: OS << ", sext"; break; in print_details()
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| D | DAGCombiner.cpp | 2989 if (LN0->getExtensionType() != ISD::SEXTLOAD && in visitAND()
5477 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD; in CombineExtLoad()
5602 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()))) { in visitSIGN_EXTEND()
5611 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, in visitSIGN_EXTEND()
5637 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT)) { in visitSIGN_EXTEND()
5638 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, in visitSIGN_EXTEND()
5657 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()) && in visitSIGN_EXTEND()
5667 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT, in visitSIGN_EXTEND()
5936 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) { in visitZERO_EXTEND()
6280 ExtType = ISD::SEXTLOAD; in ReduceLoadWidth()
[all …]
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| D | LegalizeVectorOps.cpp | 585 case ISD::SEXTLOAD: in ExpandLoad()
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| D | LegalizeIntegerTypes.cpp | 480 N->getMemOperand(), ISD::SEXTLOAD); in PromoteIntRes_MLOAD()
1919 if (ExtType == ISD::SEXTLOAD) { in ExpandIntRes_LOAD()
1993 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, in ExpandIntRes_LOAD()
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| D | LegalizeDAG.cpp | 969 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
1130 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
3799 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, in ExpandNode()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
1221 if (Load->getExtensionType() == ISD::SEXTLOAD) { in adjustSubwordCmp()
1254 ISD::SEXTLOAD : in adjustSubwordCmp()
1282 case ISD::SEXTLOAD: in isNaturalMemoryOperand()
1438 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) { in adjustICmpTruncate()
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| D | SystemZOperators.td | 230 return Type == ISD::EXTLOAD || Type == ISD::SEXTLOAD;
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 219 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in NVPTXTargetLowering()
2150 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
2277 ISD::SEXTLOAD : ISD::ZEXTLOAD; in LowerFormalArguments()
4004 if (ExtType == ISD::SEXTLOAD) { in PerformANDCombine()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
740 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand); in X86TargetLowering()
868 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom); in X86TargetLowering()
869 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom); in X86TargetLowering()
870 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom); in X86TargetLowering()
959 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom); in X86TargetLowering()
960 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom); in X86TargetLowering()
961 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom); in X86TargetLowering()
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal); in X86TargetLowering()
966 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal); in X86TargetLowering()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 221 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MipsTargetLowering()
397 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); in MipsTargetLowering()
1563 Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, in lowerBR_JT()
2180 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || in lowerLOAD()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 133 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 986 else if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
996 if (ExtType == ISD::SEXTLOAD) { in SelectIndexedLoad()
1009 if (ExtType == ISD::SEXTLOAD) { in SelectIndexedLoad()
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| D | AArch64ISelLowering.cpp | 436 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand); in AArch64TargetLowering()
599 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand); in AArch64TargetLowering()
2190 ExtType = ISD::SEXTLOAD; in LowerFormalArguments()
8311 ExtType = ISD::SEXTLOAD; in checkValueWidth()
8412 if (ExtType == ISD::SEXTLOAD) in isEquivalentMaskless()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1469 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) in SelectARMIndexedLoad()
1473 if (LD->getExtensionType() == ISD::SEXTLOAD) { in SelectARMIndexedLoad()
1522 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; in SelectT2IndexedLoad()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 470 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; in LowerFormalArguments_32()
1388 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SparcTargetLowering()
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