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Searched refs:SINT_TO_FP (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp105 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
108 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, in getCastInstrCost()
112 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
114 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }, in getCastInstrCost()
116 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
118 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
122 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 }, in getCastInstrCost()
124 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i16, 8 }, in getCastInstrCost()
[all …]
DARMISelLowering.cpp109 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
114 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in addTypeForNEON()
532 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
618 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
3835 case ISD::SINT_TO_FP: in LowerVectorINT_TO_FP()
3837 Opc = ISD::SINT_TO_FP; in LowerVectorINT_TO_FP()
3855 if (Op.getOpcode() == ISD::SINT_TO_FP) in LowerINT_TO_FP()
5961 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); in LowerSDIV_v4i8()
5962 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); in LowerSDIV_v4i8()
5991 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); in LowerSDIV_v4i16()
[all …]
/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp473 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 2*10 }, in getCastInstrCost()
474 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v4i32, 4*10 }, in getCastInstrCost()
475 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v8i16, 8*10 }, in getCastInstrCost()
476 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v16i8, 16*10 }, in getCastInstrCost()
482 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v2i64, 15 }, in getCastInstrCost()
483 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 15 }, in getCastInstrCost()
484 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v8i16, 15 }, in getCastInstrCost()
485 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v16i8, 8 }, in getCastInstrCost()
519 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
520 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i8, 2 }, in getCastInstrCost()
[all …]
DREADME-FPStack.txt49 Add a target specific hook to DAG combiner to handle SINT_TO_FP and
DX86ISelLowering.cpp197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); in X86TargetLowering()
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); in X86TargetLowering()
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
205 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); in X86TargetLowering()
207 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); in X86TargetLowering()
208 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); in X86TargetLowering()
211 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
212 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); in X86TargetLowering()
218 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); in X86TargetLowering()
729 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in X86TargetLowering()
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/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp192 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
194 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
200 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
201 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
202 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
208 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 }, in getCastInstrCost()
209 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
214 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
215 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, in getCastInstrCost()
[all …]
DAArch64ISelLowering.cpp192 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
193 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
194 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
478 setTargetDAGCombine(ISD::SINT_TO_FP); in AArch64TargetLowering()
548 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
557 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote); in AArch64TargetLowering()
559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote); in AArch64TargetLowering()
562 setOperationAction(ISD::SINT_TO_FP, MVT::v8i8, Promote); in AArch64TargetLowering()
564 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote); in AArch64TargetLowering()
567 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); in AArch64TargetLowering()
[all …]
/external/llvm/test/CodeGen/R600/
Ddagcombiner-bug-illegal-vec4-int-to-fp.ll7 ; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp329 case ISD::SINT_TO_FP: in LegalizeOp()
370 case ISD::SINT_TO_FP: in Promote()
934 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || in ExpandUINT_TO_FLOAT()
960 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); in ExpandUINT_TO_FLOAT()
962 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); in ExpandUINT_TO_FLOAT()
DLegalizeFloatTypes.cpp103 case ISD::SINT_TO_FP: in SoftenFloatResult()
637 bool Signed = N->getOpcode() == ISD::SINT_TO_FP; in SoftenFloatRes_XINT_TO_FP()
914 case ISD::SINT_TO_FP: in ExpandFloatResult()
1279 bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; in ExpandFloatRes_XINT_TO_FP()
1291 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); in ExpandFloatRes_XINT_TO_FP()
1771 case ISD::SINT_TO_FP: in PromoteFloatResult()
DLegalizeDAG.cpp1192 case ISD::SINT_TO_FP: in LegalizeOp()
2506 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); in ExpandLegalINT_TO_FP()
2515 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); in ExpandLegalINT_TO_FP()
2558 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); in ExpandLegalINT_TO_FP()
2624 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { in PromoteLegalINT_TO_FP()
2625 OpToUse = ISD::SINT_TO_FP; in PromoteLegalINT_TO_FP()
3036 case ISD::SINT_TO_FP: in ExpandNode()
3038 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, in ExpandNode()
4032 Node->getOpcode() == ISD::SINT_TO_FP || in PromoteNode()
4084 case ISD::SINT_TO_FP: in PromoteNode()
[all …]
DLegalizeVectorTypes.cpp96 case ISD::SINT_TO_FP: in ScalarizeVectorResult()
432 case ISD::SINT_TO_FP: in ScalarizeVectorOperand()
637 case ISD::SINT_TO_FP: in SplitVectorResult()
1317 case ISD::SINT_TO_FP: in SplitVectorOperand()
1788 case ISD::SINT_TO_FP: in WidenVectorResult()
2640 case ISD::SINT_TO_FP: in WidenVectorOperand()
DSelectionDAGDumper.cpp238 case ISD::SINT_TO_FP: return "sint_to_fp"; in getOperationName()
DLegalizeIntegerTypes.cpp854 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break; in PromoteIntegerOperand()
2524 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break; in ExpandIntegerOperand()
2847 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ in ExpandIntOp_UINT_TO_FP()
2849 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op); in ExpandIntOp_UINT_TO_FP()
DFastISel.cpp243 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1560 return selectCast(I, ISD::SINT_TO_FP); in selectOperator()
DDAGCombiner.cpp1356 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); in visit()
7949 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); in visitSINT_TO_FP()
7953 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && in visitSINT_TO_FP()
8006 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { in visitUINT_TO_FP()
8009 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); in visitUINT_TO_FP()
8035 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP) in FoldIntToFPToInt()
8040 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP; in FoldIntToFPToInt()
11283 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { in reduceBuildVecConvertToConvertBuildVec()
11306 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) in reduceBuildVecConvertToConvertBuildVec()
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h384 SINT_TO_FP, enumerator
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp527 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia); in LowerSDIV24()
530 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib); in LowerSDIV24()
DR600ISelLowering.cpp414 ConversionOp = ISD::SINT_TO_FP; in LowerSELECT_CC()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1454 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1459 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1464 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
1469 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in HexagonTargetLowering()
1474 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal); in HexagonTargetLowering()
1487 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in HexagonTargetLowering()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
106 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
112 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
499 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
608 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
[all …]
/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp299 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
328 setOperationAction(ISD::SINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
618 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); in LowerOperation()
1550 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
2153 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1422 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1424 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
2798 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, in LowerOperation()
3205 case ISD::SINT_TO_FP: in ReplaceNodeResults()
3212 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1559 case SIToFP: return ISD::SINT_TO_FP; in InstructionOpcodeToISD()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp281 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); in addMSAIntType()
1833 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()

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