Home
last modified time | relevance | path

Searched refs:SimpleTy (Results 1 – 25 of 45) sorted by relevance

12

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h162 SimpleValueType SimpleTy; variable
164 LLVM_CONSTEXPR MVT() : SimpleTy(INVALID_SIMPLE_VALUE_TYPE) {} in MVT()
165 LLVM_CONSTEXPR MVT(SimpleValueType SVT) : SimpleTy(SVT) { } in MVT()
167 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
168 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
169 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
170 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
171 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
172 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
176 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
[all …]
DValueTypes.h45 if (V.SimpleTy != VT.V.SimpleTy)
47 if (V.SimpleTy < 0)
63 if (M.SimpleTy >= 0) in getIntegerVT()
72 if (M.SimpleTy >= 0) in getVectorVT()
87 assert(VecTy.SimpleTy >= 0 && in changeVectorElementTypeToInteger()
95 return V.SimpleTy >= 0; in isSimple()
325 return V.SimpleTy; in getRawBits()
334 if (L.V.SimpleTy == R.V.SimpleTy) in operator()
337 return L.V.SimpleTy < R.V.SimpleTy; in operator()
/external/llvm/include/llvm/Target/
DTargetLowering.h365 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in getRegClassFor()
378 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; in getRepRegClassFor()
385 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
393 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); in isTypeLegal()
394 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; in isTypeLegal()
408 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy]; in getTypeAction()
412 unsigned I = VT.SimpleTy; in setTypeAction()
537 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy; in getOperationAction()
577 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getLoadExtAction()
578 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.h92 if (LocVT.SimpleTy == MVT::i64) in CC_AArch64_Custom_Block()
94 else if (LocVT.SimpleTy == MVT::f16) in CC_AArch64_Custom_Block()
96 else if (LocVT.SimpleTy == MVT::f32 || LocVT.is32BitVector()) in CC_AArch64_Custom_Block()
98 else if (LocVT.SimpleTy == MVT::f64 || LocVT.is64BitVector()) in CC_AArch64_Custom_Block()
100 else if (LocVT.SimpleTy == MVT::f128 || LocVT.is128BitVector()) in CC_AArch64_Custom_Block()
DAArch64FastISel.cpp286 switch (VT.SimpleTy) { in getImplicitScaleFactor()
1089 switch (RetVT.SimpleTy) { in emitAddSub()
1108 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1394 switch (VT.SimpleTy) { in emitCmp()
1578 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp()
1600 switch (RetVT.SimpleTy) { in emitLogicalOp_ri()
1646 switch (RetVT.SimpleTy) { in emitLogicalOp_rs()
1750 switch (VT.SimpleTy) { in emitLoad()
1998 switch (VT.SimpleTy) { in emitStore()
2590 switch (VT.SimpleTy) { in selectSelect()
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp681 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; in SelectLoad()
922 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
946 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
975 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
999 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1029 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1053 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1076 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1100 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
1131 switch (EltVT.getSimpleVT().SimpleTy) { in SelectLoadVector()
[all …]
DNVPTXTargetTransformInfo.cpp113 if (LT.second.SimpleTy == MVT::i64) in getArithmeticInstrCost()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp335 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitLoad()
420 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
487 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore()
1115 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode()
1132 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode()
1295 if (SrcVT.SimpleTy == MVT::i1) { in X86SelectZExt()
1308 switch (SrcVT.SimpleTy) { in X86SelectZExt()
1435 switch (SourceVT.SimpleTy) { in X86SelectBranch()
1639 switch (VT.SimpleTy) { in X86SelectDivRem()
1683 if (VT.SimpleTy == MVT::i16) { in X86SelectDivRem()
[all …]
DX86ISelDAGToDAG.cpp1809 switch (NVT.SimpleTy) { in SelectAtomicLoadArith()
2206 switch (NVT.SimpleTy) { in Select()
2267 switch (NVT.SimpleTy) { in Select()
2296 switch (NVT.SimpleTy) { in Select()
2306 switch (NVT.SimpleTy) { in Select()
2446 switch (NVT.SimpleTy) { in Select()
2454 switch (NVT.SimpleTy) { in Select()
2465 switch (NVT.SimpleTy) { in Select()
2520 switch (NVT.SimpleTy) { in Select()
2651 switch (N0.getSimpleValueType().SimpleTy) { in Select()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DSIRegisterInfo.cpp55 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
DR600RegisterInfo.cpp110 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
DAMDILISelLowering.cpp252 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 in isFPImmLegal()
253 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { in isFPImmLegal()
263 if (VT.getScalarType().getSimpleVT().SimpleTy == MVT::f32 in ShouldShrinkFPConstant()
264 || VT.getScalarType().getSimpleVT().SimpleTy == MVT::f64) { in ShouldShrinkFPConstant()
/external/llvm/lib/Target/R600/
DR600RegisterInfo.cpp69 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
DSIRegisterInfo.cpp336 switch(VT.SimpleTy) { in getCFGStructurizerRegClass()
/external/llvm/lib/IR/
DValueTypes.cpp107 switch (V.SimpleTy) { in getEVTString()
181 switch (V.SimpleTy) { in getTypeForEVT()
/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp306 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad()
334 switch (VT.SimpleTy) { in SelectIndexedLoad()
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp624 switch (VT.SimpleTy) { in emitLoad()
685 switch (VT.SimpleTy) { in emitStore()
1317 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1335 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1359 switch (SrcVT.SimpleTy) { in emitIntZExt()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp864 switch (VT.SimpleTy) { in ARMSimplifyAddress()
919 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) in AddLoadStoreOperands()
968 switch (VT.SimpleTy) { in ARMEmitLoad()
1089 switch (VT.SimpleTy) { in ARMEmitStore()
1407 switch (SrcVT.SimpleTy) { in ARMEmitCmp()
1826 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp()
1912 switch (ArgVT.SimpleTy) { in ProcessCallArgs()
3027 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
DARMCallingConv.h205 switch (LocVT.SimpleTy) { in CC_ARM_AAPCS_Custom_Aggregate()
DARMISelDAGToDAG.cpp1528 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectT2IndexedLoad()
1790 switch (VT.getSimpleVT().SimpleTy) { in SelectVLD()
1927 switch (VT.getSimpleVT().SimpleTy) { in SelectVST()
2090 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDSTLane()
2203 switch (VT.getSimpleVT().SimpleTy) { in SelectVLDDup()
2742 switch (VT.getSimpleVT().SimpleTy) { in Select()
2762 switch (VT.getSimpleVT().SimpleTy) { in Select()
2782 switch (VT.getSimpleVT().SimpleTy) { in Select()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp670 switch (VT.SimpleTy) { \ in getATOMIC()
903 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType)); in getTypeConversion()
904 MVT NVT = TransformToType[SVT.SimpleTy]; in getTypeConversion()
1154 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in findRepresentativeClass()
1372 return getPointerTy(0).SimpleTy; in getSetCCResultType()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp214 switch (RegVT.getSimpleVT().SimpleTy) { in LowerFormalArguments()
217 << RegVT.getSimpleVT().SimpleTy << '\n'; in LowerFormalArguments()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp259 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP()
2163 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandFPLibCall()
2181 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandIntLibCall()
2196 switch (Node->getSimpleValueType(0).SimpleTy) { in isDivRemLibcallAvailable()
2241 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandDivRemLibCall()
2298 switch (Node->getSimpleValueType(0).SimpleTy) { in isSinCosLibcallAvailable()
2346 switch (Node->getSimpleValueType(0).SimpleTy) { in ExpandSinCosLibCall()
2571 switch (Op0.getSimpleValueType().SimpleTy) { in ExpandLegalINT_TO_FP()
2620 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); in PromoteLegalINT_TO_FP()
2662 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); in PromoteLegalFP_TO_INT()
[all …]
/external/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp472 if (MVT(TypeVec[i]).getVectorElementType().SimpleTy != VT) { in EnforceVectorEltTypeIs()
504 VTOperand.MergeInTypeInfo(IVT.SimpleTy, TP); in EnforceVectorEltTypeIs()
519 if (MVT(TypeVec[i]).getVectorElementType().SimpleTy != VT) { in EnforceVectorEltTypeIs()
566 EEVT::TypeSet EltTypeSet(IVT.SimpleTy, TP); in EnforceVectorSubVectorTypeIs()
590 EEVT::TypeSet EltTypeSet(IVT.SimpleTy, TP); in EnforceVectorSubVectorTypeIs()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp455 switch (VT.SimpleTy) { in PPCEmitLoad()
595 switch (VT.SimpleTy) { in PPCEmitStore()
809 switch (SrcVT.SimpleTy) { in PPCEmitCmp()

12