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Searched refs:WriteMask (Results 1 – 25 of 94) sorted by relevance

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/external/mesa3d/src/gallium/drivers/i915/
Di915_fpc_optimize.c165 o->WriteMask = i->WriteMask; in copy_dst_reg()
210 …unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) && in i915_fpc_optimize_mov_after_alu()
211 …unswizzled(&current->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) && in i915_fpc_optimize_mov_after_alu()
212 … is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) ) in i915_fpc_optimize_mov_after_alu()
218 next->FullInstruction.Dst[0].Register.WriteMask, in i915_fpc_optimize_mov_after_alu()
221 …current->FullInstruction.Dst[0].Register.WriteMask = current->FullInstruction.Dst[0].Register.Writ… in i915_fpc_optimize_mov_after_alu()
222 … next->FullInstruction.Dst[0].Register.WriteMask; in i915_fpc_optimize_mov_after_alu()
234 …unswizzled(&current->FullInstruction.Src[0], current->FullInstruction.Dst[0].Register.WriteMask) && in i915_fpc_optimize_mov_after_alu()
235 …unswizzled(&current->FullInstruction.Src[1], current->FullInstruction.Dst[0].Register.WriteMask) && in i915_fpc_optimize_mov_after_alu()
236 … is_unswizzled(&next->FullInstruction.Src[0], next->FullInstruction.Dst[0].Register.WriteMask) ) in i915_fpc_optimize_mov_after_alu()
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/external/mesa3d/src/gallium/drivers/r300/compiler/tests/
Drc_test_helpers.c203 struct match_info WriteMask; member
236 tokens.WriteMask.String = dst_str + matches[3].rm_so; in init_rc_normal_dst()
237 tokens.WriteMask.Length = match_length(matches, 3); in init_rc_normal_dst()
259 if (tokens.WriteMask.Length == 0) { in init_rc_normal_dst()
260 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in init_rc_normal_dst()
263 if (tokens.WriteMask.String[0] != '.') { in init_rc_normal_dst()
267 for (i = 1; i < tokens.WriteMask.Length; i++) { in init_rc_normal_dst()
268 switch(tokens.WriteMask.String[i]) { in init_rc_normal_dst()
270 inst->U.I.DstReg.WriteMask |= RC_MASK_X; in init_rc_normal_dst()
273 inst->U.I.DstReg.WriteMask |= RC_MASK_Y; in init_rc_normal_dst()
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/external/mesa3d/src/gallium/drivers/r300/compiler/
Dradeon_pair_translate.c90 *needrgb = (inst->DstReg.WriteMask & RC_MASK_XYZ) ? 1 : 0; in classify_instruction()
91 *needalpha = (inst->DstReg.WriteMask & RC_MASK_W) ? 1 : 0; in classify_instruction()
275 inst->DstReg.WriteMask); in set_pair_instruction()
286 pair->Alpha.DepthWriteMask |= GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
293 inst->DstReg.WriteMask & RC_MASK_XYZ; in set_pair_instruction()
295 GET_BIT(inst->DstReg.WriteMask, 3); in set_pair_instruction()
303 pair->RGB.WriteMask |= inst->DstReg.WriteMask & RC_MASK_XYZ; in set_pair_instruction()
307 pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask, 3) << 3); in set_pair_instruction()
308 if (pair->Alpha.WriteMask) { in set_pair_instruction()
Dradeon_program_tex.c92 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; in projective_divide()
173 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in radeonTransformTEX()
183 inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX()
194 inst_mul->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX()
210 inst_add->U.I.DstReg.WriteMask = RC_MASK_W; in radeonTransformTEX()
311 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
333 inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
342 inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
353 inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
368 inst_add->U.I.DstReg.WriteMask = RC_MASK_XYZ; in radeonTransformTEX()
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Dradeon_dataflow_deadcode.c41 unsigned char WriteMask:4; member
162 usedmask = *pused & inst->U.I.DstReg.WriteMask; in update_instruction()
167 insts->WriteMask |= usedmask; in update_instruction()
257 ptr->U.I.DstReg.WriteMask, srcmasks); in rc_dataflow_deadcode()
324 inst->U.I.DstReg.WriteMask = s.Instructions[ip].WriteMask; in rc_dataflow_deadcode()
325 if (s.Instructions[ip].WriteMask) in rc_dataflow_deadcode()
341 usemask = s.Instructions[ip].WriteMask; in rc_dataflow_deadcode()
Dradeon_variable.c60 if (var_ptr->Dst.WriteMask == RC_MASK_W) { in rc_variable_change_dst()
156 unsigned int mask = var->Readers[i].WriteMask; in rc_variable_compute_live_intervals()
285 new->Dst.WriteMask = DstWriteMask; in rc_variable()
332 if (sub_inst->WriteMask) { in get_variable_pair_helper()
334 writemask = sub_inst->WriteMask; in get_variable_pair_helper()
373 inst->U.I.DstReg.WriteMask, &reader_data); in rc_get_variables()
394 writemask |= var->Dst.WriteMask; in rc_variable_writemask_sum()
525 var->Inst->IP, var->Dst.Index, var->Dst.WriteMask); in rc_variable_print()
Dr3xx_fragprog.c64 if (inst->DstReg.WriteMask & RC_MASK_Z) { in rc_rewrite_depth_out()
65 inst->DstReg.WriteMask = RC_MASK_W; in rc_rewrite_depth_out()
67 inst->DstReg.WriteMask = 0; in rc_rewrite_depth_out()
Dradeon_program_alu.c104 dst.WriteMask = mask; in dstregtmpmask()
226 return dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask); in try_to_reuse_dst()
370 if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) { in transform_LIT()
379 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in transform_LIT()
445 tempdst.WriteMask = RC_MASK_W; in transform_POW()
467 unsigned int mask = inst->U.I.DstReg.WriteMask; in transform_ROUND()
600 dstregtmpmask(tmp1, inst->U.I.DstReg.WriteMask), in transform_SSG()
766 dst.WriteMask = RC_MASK_XYZW; in transform_r300_vertex_fix_LIT()
788 dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask), in transform_r300_vertex_SEQ()
815 dstregtmpmask(tmp, inst->U.I.DstReg.WriteMask), in transform_r300_vertex_SNE()
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Dradeon_program_print.c164 if (dst.WriteMask != RC_MASK_XYZW) { in rc_print_dst_register()
166 rc_print_mask(f, dst.WriteMask); in rc_print_dst_register()
389 if (inst->RGB.WriteMask) in rc_print_pair_instruction()
391 (inst->RGB.WriteMask & 1) ? "x" : "", in rc_print_pair_instruction()
392 (inst->RGB.WriteMask & 2) ? "y" : "", in rc_print_pair_instruction()
393 (inst->RGB.WriteMask & 4) ? "z" : ""); in rc_print_pair_instruction()
428 if (inst->Alpha.WriteMask) in rc_print_pair_instruction()
Dradeon_dataflow.c261 if (opcode->HasDstReg && inst->DstReg.WriteMask) in writes_normal()
262 cb(userdata, fullinst, inst->DstReg.File, inst->DstReg.Index, inst->DstReg.WriteMask); in writes_normal()
272 if (inst->RGB.WriteMask) in writes_pair()
273 cb(userdata, fullinst, RC_FILE_TEMPORARY, inst->RGB.DestIndex, inst->RGB.WriteMask); in writes_pair()
275 if (inst->Alpha.WriteMask) in writes_pair()
394 if (inst->RGB.WriteMask) { in remap_pair_instruction()
403 if (inst->Alpha.WriteMask) { in remap_pair_instruction()
486 new->WriteMask = mask; in add_reader()
888 if (sub_writer->WriteMask) { in rc_get_readers_sub()
890 sub_writer->DestIndex, sub_writer->WriteMask); in rc_get_readers_sub()
Dradeon_optimize.c441 reader_data->Writer->U.I.DstReg.WriteMask, in presub_scan_read()
566 unsigned dstmask = inst_add->U.I.DstReg.WriteMask; in peephole_add_presub_add()
640 if(((1 << i) & inst_add->U.I.DstReg.WriteMask) in peephole_add_presub_inv()
647 if ((inst_add->U.I.SrcReg[1].Negate & inst_add->U.I.DstReg.WriteMask) != in peephole_add_presub_inv()
648 inst_add->U.I.DstReg.WriteMask in peephole_add_presub_inv()
678 d->Writer->File, d->Writer->Index, d->Writer->WriteMask)) { in omod_filter_reader_cb()
693 (mask & d->Writer->WriteMask)) { in omod_filter_writer_cb()
821 writer->Inst->U.I.DstReg.WriteMask, in peephole_mul_omod()
822 inst_mul->U.I.DstReg.WriteMask); in peephole_mul_omod()
Dradeon_emulate_branches.c78 inst_mov->U.I.DstReg.WriteMask = RC_MASK_X; in handle_if()
168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in allocate_and_insert_proxies()
187 inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW; in inject_cmp()
298 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW; in fix_output_writes()
Dr3xx_vertprog.c195 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector1()
211 t_dst_mask(vpi->DstReg.WriteMask), in ei_vector2()
227 t_dst_mask(vpi->DstReg.WriteMask), in ei_math1()
244 t_dst_mask(vpi->DstReg.WriteMask), in ei_lit()
311 t_dst_mask(vpi->DstReg.WriteMask), in ei_mad()
318 t_dst_mask(vpi->DstReg.WriteMask), in ei_mad()
351 t_dst_mask(vpi->DstReg.WriteMask), in ei_pow()
755 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW; in rc_vs_add_artificial_outputs()
799 add->U.I.DstReg.WriteMask = RC_MASK_X; in transform_negative_addressing()
/external/mesa3d/src/mesa/program/
Dprog_instruction.c54 inst[i].DstReg.WriteMask = WRITEMASK_XYZW; in _mesa_init_instructions()
307 if (inst->DstReg.WriteMask == WRITEMASK_X || in _mesa_check_soa_dependencies()
308 inst->DstReg.WriteMask == WRITEMASK_Y || in _mesa_check_soa_dependencies()
309 inst->DstReg.WriteMask == WRITEMASK_Z || in _mesa_check_soa_dependencies()
310 inst->DstReg.WriteMask == WRITEMASK_W || in _mesa_check_soa_dependencies()
311 inst->DstReg.WriteMask == 0x0) { in _mesa_check_soa_dependencies()
323 if (inst->DstReg.WriteMask & (1 << chan)) { in _mesa_check_soa_dependencies()
Dprog_optimize.c88 channel_mask = inst->DstReg.WriteMask & dst_mask; in get_src_arg_mask()
134 const GLuint mask = mov->DstReg.WriteMask; in get_dst_mask_for_mov()
331 inst->DstReg.WriteMask & (1 << chan)) { in _mesa_remove_dead_code_global()
336 inst->DstReg.WriteMask &= ~(1 << chan); in _mesa_remove_dead_code_global()
341 if (inst->DstReg.WriteMask == 0) { in _mesa_remove_dead_code_global()
421 mask &= ~inst->DstReg.WriteMask; in find_next_use()
523 dst_mask = mov->DstReg.WriteMask; in _mesa_remove_extra_move_use()
573 dst_mask &= ~inst2->DstReg.WriteMask; in _mesa_remove_extra_move_use()
581 src_mask &= ~inst2->DstReg.WriteMask; in _mesa_remove_extra_move_use()
613 const GLuint mask = inst->DstReg.WriteMask; in _mesa_remove_dead_code_local()
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Dprogramopt.c93 newInst[i].DstReg.WriteMask = (WRITEMASK_X << i); in _mesa_insert_mvp_dp4_code()
165 newInst[0].DstReg.WriteMask = WRITEMASK_XYZW; in _mesa_insert_mvp_mad_code()
177 newInst[i].DstReg.WriteMask = WRITEMASK_XYZW; in _mesa_insert_mvp_mad_code()
192 newInst[3].DstReg.WriteMask = WRITEMASK_XYZW; in _mesa_insert_mvp_mad_code()
324 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
345 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
359 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
372 inst->DstReg.WriteMask = WRITEMASK_X; in _mesa_append_fog_code()
384 inst->DstReg.WriteMask = WRITEMASK_XYZ; in _mesa_append_fog_code()
399 inst->DstReg.WriteMask = WRITEMASK_W; in _mesa_append_fog_code()
/external/mesa3d/src/mesa/main/
Dstencil.c276 if (ctx->Stencil.WriteMask[face] == mask) in _mesa_StencilMask()
279 ctx->Stencil.WriteMask[face] = mask; in _mesa_StencilMask()
290 if (ctx->Stencil.WriteMask[0] == mask && in _mesa_StencilMask()
291 ctx->Stencil.WriteMask[1] == mask) in _mesa_StencilMask()
294 ctx->Stencil.WriteMask[0] = ctx->Stencil.WriteMask[1] = mask; in _mesa_StencilMask()
536 ctx->Stencil.WriteMask[0] = mask; in _mesa_StencilMaskSeparate()
539 ctx->Stencil.WriteMask[1] = mask; in _mesa_StencilMaskSeparate()
566 ctx->Stencil.WriteMask[0] != ctx->Stencil.WriteMask[face]); in _mesa_update_stencil()
601 ctx->Stencil.WriteMask[0] = ~0U; in _mesa_init_stencil()
602 ctx->Stencil.WriteMask[1] = ~0U; in _mesa_init_stencil()
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/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen6_depthstencil.c60 ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0]; in gen6_upload_depth_stencil_state()
73 ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back]; in gen6_upload_depth_stencil_state()
79 if (ctx->Stencil.WriteMask[0] || in gen6_upload_depth_stencil_state()
80 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back])) in gen6_upload_depth_stencil_state()
Dbrw_wm_fp.c139 reg.WriteMask = WRITEMASK_XYZW; in dst_reg()
149 reg.WriteMask &= mask; in dst_mask()
260 if (inst0->DstReg.WriteMask == 0) in emit_scalar_insn()
263 dst_chan = ffs(inst0->DstReg.WriteMask) - 1; in emit_scalar_insn()
266 inst->DstReg.WriteMask = 1 << dst_chan; in emit_scalar_insn()
268 other_channel_mask = inst0->DstReg.WriteMask & ~(1 << dst_chan); in emit_scalar_insn()
564 if (dst.WriteMask & WRITEMASK_Y) { in precalc_dst()
576 if (dst.WriteMask & WRITEMASK_XZ) { in precalc_dst()
592 if (dst.WriteMask & WRITEMASK_W) { in precalc_dst()
626 if (dst.WriteMask & WRITEMASK_YZ) { in precalc_lit()
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Dbrw_cc.c120 cc->cc1.stencil_write_mask = ctx->Stencil.WriteMask[0]; in upload_cc_unit()
134 cc->cc2.bf_stencil_write_mask = ctx->Stencil.WriteMask[back]; in upload_cc_unit()
140 if (ctx->Stencil.WriteMask[0] || in upload_cc_unit()
141 (ctx->Stencil._TestTwoSide && ctx->Stencil.WriteMask[back])) in upload_cc_unit()
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_exec.c585 uint writemask = inst->Dst[0].Register.WriteMask; in tgsi_check_soa_dependencies()
606 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in tgsi_check_soa_dependencies()
1908 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_tex()
1987 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txd()
2059 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txf()
2088 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_txq()
2200 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_sample()
2263 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_sample_d()
2424 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_vector()
2450 if (inst->Dst[0].Register.WriteMask & (1 << chan)) { in exec_scalar_unary()
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/external/mesa3d/src/gallium/auxiliary/draw/
Ddraw_pipe_aapoint.c245 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XY; in aa_transform_inst()
259 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X; in aa_transform_inst()
276 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X; in aa_transform_inst()
288 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_X; in aa_transform_inst()
301 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y; in aa_transform_inst()
334 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z; in aa_transform_inst()
350 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Z; in aa_transform_inst()
363 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y; in aa_transform_inst()
379 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_W; in aa_transform_inst()
395 newInst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_Y; in aa_transform_inst()
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/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_vertprog.c696 dst.WriteMask & WRITEMASK_X) { in r200_translate_vertex_program()
712 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
741 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
758 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
777 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
803 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
826 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
841 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
856 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
875 t_dst_mask(dst.WriteMask)); in r200_translate_vertex_program()
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/external/mesa3d/src/gallium/drivers/r600/
Dr600_shader.c1784 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); in tgsi_op2_s()
1787 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) in tgsi_op2_s()
1843 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask); in tgsi_ineg()
1847 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) in tgsi_ineg()
1874 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3; in cayman_emit_float_instr()
1888 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1; in cayman_emit_float_instr()
1904 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3; in cayman_mul_int_instr()
1906 if (!(inst->Dst[0].Register.WriteMask & (1 << k))) in cayman_mul_int_instr()
2011 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3; in cayman_trig()
2025 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1; in cayman_trig()
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/external/mesa3d/src/mesa/state_tracker/
Dst_atom_depth.c118 dsa->stencil[0].writemask = ctx->Stencil.WriteMask[0] & 0xff; in update_depth_stencil_alpha()
129 dsa->stencil[1].writemask = ctx->Stencil.WriteMask[back] & 0xff; in update_depth_stencil_alpha()

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