| /external/llvm/test/CodeGen/Mips/ |
| D | mips64muldiv.ll | 44 ; ACC: ddivu $zero, $4, $5
46 ; GPR: ddivu $2, $4, $5
64 ; ACC: ddivu $zero, $4, $5
|
| D | mips64instrs.ll | 140 ; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]
144 ; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]
172 ; ACCMULDIV: ddivu $zero, $4, $5
|
| D | divrem.ll | 285 ; GPR64: ddivu $2, $4, $5
366 ; ACC64: ddivu $zero, $4, $5
378 ; GPR64-DAG: ddivu $2, $4, $5
|
| /external/v8/test/cctest/ |
| D | test-disasm-mips64.cc | 171 COMPARE(ddivu(a0, a1), in TEST()
173 COMPARE(ddivu(a6, a7), in TEST()
175 COMPARE(ddivu(v0, v1), in TEST()
263 COMPARE(ddivu(a0, a1, a2), in TEST()
271 COMPARE(ddivu(a5, a6, a7), in TEST()
279 COMPARE(ddivu(v0, v1, a0), in TEST()
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | udiv.ll | 94 ; GP64-NOT-R6: ddivu $zero, $4, $5
98 ; 64R6: ddivu $2, $4, $5
|
| D | urem.ll | 133 ; GP64-NOT-R6: ddivu $zero, $4, $5
|
| /external/valgrind/none/tests/mips64/ |
| D | arithmetic_instruction.stdout.exp-mips64r2 | 9467 ddivu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
9468 ddivu $v0, $v1 :: rs 0x12bd6aa, rt 0xa2a6ec661ba84121, HI 0x12bd6aa, LO 0x0
9469 ddivu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
9470 ddivu $v0, $v1 :: rs 0x7e876382d2ab13, rt 0x614d9b445f12236b, HI 0x7e876382d2ab13, LO 0x0
9471 ddivu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
9472 ddivu $v0, $v1 :: rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75, HI 0x20183c0c843a7609, LO 0x2
9473 ddivu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
9474 ddivu $v0, $v1 :: rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666, HI 0x4f679f17a89fef95, LO 0x1
9475 ddivu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
9476 ddivu $v0, $v1 :: rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17, HI 0x42b0c0a28677b502, LO 0x0
[all …]
|
| D | arithmetic_instruction.stdout.exp-mips64 | 9467 ddivu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
9468 ddivu $v0, $v1 :: rs 0x12bd6aa, rt 0xa2a6ec661ba84121, HI 0x12bd6aa, LO 0x0
9469 ddivu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
9470 ddivu $v0, $v1 :: rs 0x7e876382d2ab13, rt 0x614d9b445f12236b, HI 0x7e876382d2ab13, LO 0x0
9471 ddivu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
9472 ddivu $v0, $v1 :: rs 0x976d6e9ac31510f3, rt 0x3baa99471f6d4d75, HI 0x20183c0c843a7609, LO 0x2
9473 ddivu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
9474 ddivu $v0, $v1 :: rs 0xb7746d775ad6a5fb, rt 0x680cce5fb236b666, HI 0x4f679f17a89fef95, LO 0x1
9475 ddivu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
9476 ddivu $v0, $v1 :: rs 0x42b0c0a28677b502, rt 0x58ec644d6481af17, HI 0x42b0c0a28677b502, LO 0x0
[all …]
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| D | mips64_le.txt | 11 # CHECK: ddivu $zero, $9, $24
|
| D | mips64r2_le.txt | 11 # CHECK: ddivu $zero, $9, $24
|
| D | mips64r2.txt | 11 # CHECK: ddivu $zero, $9, $24
|
| D | mips64.txt | 14 # CHECK: ddivu $zero, $9, $24
|
| D | mips64r6.txt | 99 0x00 0x64 0x10 0x9f # CHECK: ddivu $2, $3, $4
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips3.s | 31 # ddivu has been re-encoded. See valid.s
|
| D | invalid-mips64.s | 52 # ddivu has been re-encoded. See valid.s
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips3.s | 21 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
|
| D | invalid-mips5.s | 21 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
|
| D | invalid-mips4.s | 21 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | invalid-mips3.s | 25 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
| D | invalid-mips4.s | 23 …ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips64r6InstrInfo.td | 64 class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>;
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 71 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 75 ddivu $zero,$s0,$s1
|
| /external/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 75 ddivu $zero,$s0,$s1
|
| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 748 void ddivu(Register rs, Register rt);
752 void ddivu(Register rd, Register rs, Register rt);
|