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Searched refs:divu (Results 1 – 25 of 65) sorted by relevance

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/external/llvm/test/CodeGen/Mips/llvm-ir/
Dudiv.ll32 ; NOT-R6: divu $zero, $4, $5
36 ; R6: divu $2, $4, $5
47 ; NOT-R6: divu $zero, $4, $5
51 ; R6: divu $2, $4, $5
62 ; NOT-R6: divu $zero, $4, $5
66 ; R6: divu $2, $4, $5
77 ; NOT-R6: divu $zero, $4, $5
81 ; R6: divu $2, $4, $5
Durem.ll37 ; NOT-R6: divu $zero, $[[T1]], $[[T0]]
60 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
68 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
89 ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]]
97 ; R2-R5: divu $zero, $[[T1]], $[[T0]]
116 ; NOT-R6: divu $zero, $4, $5
/external/llvm/test/CodeGen/Mips/
Ddivrem.ll88 ; ACC32: divu $zero, $4, $5
91 ; ACC64: divu $zero, $4, $5
94 ; GPR32: divu $2, $4, $5
97 ; GPR64: divu $2, $4, $5
114 ; ACC32: divu $zero, $4, $5
117 ; ACC64: divu $zero, $4, $5
182 ; ACC32: divu $zero, $4, $5
189 ; ACC64: divu $zero, $4, $5
200 ; GPR32-DAG: divu $2, $4, $5
208 ; GPR64-DAG: divu $2, $4, $5
[all …]
Ddivu.ll12 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
Dremu.ll13 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
Ddivu_remu.ll16 ; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
/external/v8/test/cctest/
Dtest-disasm-mips.cc135 COMPARE(divu(a0, a1), in TEST()
137 COMPARE(divu(t2, t3), in TEST()
139 COMPARE(divu(v0, v1), in TEST()
190 COMPARE(divu(a0, a1, a2), in TEST()
194 COMPARE(divu(t1, t2, t3), in TEST()
198 COMPARE(divu(v0, v1, a0), in TEST()
Dtest-disasm-mips64.cc165 COMPARE(divu(a0, a1), in TEST()
167 COMPARE(divu(a6, a7), in TEST()
169 COMPARE(divu(v0, v1), in TEST()
259 COMPARE(divu(a0, a1, a2), in TEST()
267 COMPARE(divu(a5, a6, a7), in TEST()
275 COMPARE(divu(v0, v1, a0), in TEST()
/external/llvm/test/MC/Mips/
Dmicromips-alu-instructions.s40 # CHECK-EL: divu $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xbb]
77 # CHECK-EB: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c]
112 divu $0, $9, $7
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips1.s26 # divu has been re-encoded. See valid.s
Dinvalid-mips2.s38 # divu has been re-encoded. See valid.s
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips3.s33 # divu has been re-encoded. See valid.s
Dinvalid-mips1.s29 # divu has been re-encoded. See valid.s
Dinvalid-mips2.s41 # divu has been re-encoded. See valid.s
Dinvalid-mips64.s54 # divu has been re-encoded. See valid.s
/external/llvm/test/MC/Mips/mips1/
Dvalid.s42 divu $zero,$25,$15
/external/valgrind/none/tests/mips64/
Darithmetic_instruction.stdout.exp-mips64r210223 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
10224 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
10225 divu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
10226 divu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
10227 divu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
10228 divu $t0, $t1 :: rs 0x17c56b6b, rt 0xffffffffa6322bdf, HI 0x17c56b6b, LO 0x0
10229 divu $t0, $t1 :: rs 0x1a864db2, rt 0xffffffffab710d06, HI 0x1a864db2, LO 0x0
10230 divu $t0, $t1 :: rs 0x1e475005, rt 0xffffffffafb010b1, HI 0x1e475005, LO 0x0
10231 divu $t0, $t1 :: rs 0x2608edb8, rt 0xffffffff97ffad0c, HI 0x2608edb8, LO 0x0
10232 divu $t0, $t1 :: rs 0x22c9f00f, rt 0xffffffff933eb0bb, HI 0x22c9f00f, LO 0x0
[all …]
Darithmetic_instruction.stdout.exp-mips6410223 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb1f740b4, HI 0x0, LO 0x0
10224 divu $t0, $t1 :: rs 0x0, rt 0xffffffffb5365d03, HI 0x0, LO 0x0
10225 divu $t0, $t1 :: rs 0x9823b6e, rt 0xffffffffb8757bda, HI 0x9823b6e, LO 0x0
10226 divu $t0, $t1 :: rs 0xd4326d9, rt 0xffffffffbcb4666d, HI 0xd4326d9, LO 0x0
10227 divu $t0, $t1 :: rs 0x130476dc, rt 0xffffffffa2f33668, HI 0x130476dc, LO 0x0
10228 divu $t0, $t1 :: rs 0x17c56b6b, rt 0xffffffffa6322bdf, HI 0x17c56b6b, LO 0x0
10229 divu $t0, $t1 :: rs 0x1a864db2, rt 0xffffffffab710d06, HI 0x1a864db2, LO 0x0
10230 divu $t0, $t1 :: rs 0x1e475005, rt 0xffffffffafb010b1, HI 0x1e475005, LO 0x0
10231 divu $t0, $t1 :: rs 0x2608edb8, rt 0xffffffff97ffad0c, HI 0x2608edb8, LO 0x0
10232 divu $t0, $t1 :: rs 0x22c9f00f, rt 0xffffffff933eb0bb, HI 0x22c9f00f, LO 0x0
[all …]
/external/llvm/test/MC/Mips/mips2/
Dvalid.s56 divu $zero,$25,$15
/external/llvm/test/MC/Disassembler/Mips/mips1/
Dvalid-mips1.txt42 0x03 0x2f 0x00 0x1b # CHECK: divu $zero, $25, $15
Dvalid-mips1-el.txt42 0x1b 0x00 0x2f 0x03 # CHECK: divu $zero, $25, $15
/external/llvm/test/MC/Mips/mips32/
Dvalid.s64 divu $zero,$25,$15
/external/llvm/test/MC/Disassembler/Mips/
Dmicromips.txt115 # CHECK-EB: divu $zero, $9, $7
Dmicromips_le.txt115 # CHECK: divu $zero, $9, $7
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s68 divu $zero,$25,$15

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