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Searched refs:getLocReg (Results 1 – 20 of 20) sorted by relevance

/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp222 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
334 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
418 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
423 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
456 Chain = DAG.getCopyFromReg(Chain, DL, Val.getLocReg(), in LowerCallResult()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), in LowerReturn_32()
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
296 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { in LowerReturn_64()
304 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); in LowerReturn_64()
308 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
379 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments_32()
394 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments_32()
405 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments_32()
566 unsigned VReg = MF.addLiveIn(VA.getLocReg(), in LowerFormalArguments_64()
820 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); in LowerCall_32()
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/external/llvm/lib/Target/ARM/
DARMFastISel.cpp1986 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg); in ProcessCallArgs()
1987 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
1999 TII.get(ARM::VMOVRRD), VA.getLocReg()) in ProcessCallArgs()
2000 .addReg(NextVA.getLocReg(), RegState::Define) in ProcessCallArgs()
2002 RegArgs.push_back(VA.getLocReg()); in ProcessCallArgs()
2003 RegArgs.push_back(NextVA.getLocReg()); in ProcessCallArgs()
2049 .addReg(RVLocs[0].getLocReg()) in FinishCall()
2050 .addReg(RVLocs[1].getLocReg())); in FinishCall()
2052 UsedRegs.push_back(RVLocs[0].getLocReg()); in FinishCall()
2053 UsedRegs.push_back(RVLocs[1].getLocReg()); in FinishCall()
[all …]
DARMISelLowering.cpp1359 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1364 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
1378 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1382 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); in LowerCallResult()
1392 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), in LowerCallResult()
1438 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id))); in PassF64ArgInRegs()
1441 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id))); in PassF64ArgInRegs()
1583 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2059 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) in IsEligibleForTailCallOptimization()
2225 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
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/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp1030 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
1031 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
1096 ResultReg).addReg(RVLocs[0].getLocReg()); in finishCall()
1097 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
1220 unsigned DestReg = VA.getLocReg(); in selectRet()
1256 RetRegs.push_back(VA.getLocReg()); in selectRet()
DMipsISelLowering.cpp2633 unsigned LocRegLo = VA.getLocReg(); in LowerCall()
2675 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2785 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), in LowerCallResult()
2951 unsigned ArgReg = VA.getLocReg(); in LowerFormalArguments()
3127 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); in LowerReturn()
3131 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp469 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
553 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), in LowerReturn()
559 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
628 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
733 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), in LowerCallResult()
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp222 Regs.push_back(MCPhysReg(Locs[I].getLocReg())); in getRemainingRegParmsForType()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1012 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1041 unsigned DstReg = VA.getLocReg(); in X86SelectRet()
1050 RetRegs.push_back(VA.getLocReg()); in X86SelectRet()
2985 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in fastLowerCall()
2986 OutRegs.push_back(VA.getLocReg()); in fastLowerCall()
3149 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in fastLowerCall()
3157 TII.get(TargetOpcode::COPY), CopyReg).addReg(VA.getLocReg()); in fastLowerCall()
3158 InRegs.push_back(VA.getLocReg()); in fastLowerCall()
DX86ISelLowering.cpp1914 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && in LowerReturn()
1927 if (VA.getLocReg() == X86::FP0 || in LowerReturn()
1928 VA.getLocReg() == X86::FP1) { in LowerReturn()
1942 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { in LowerReturn()
1954 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); in LowerReturn()
1956 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
2076 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) && in LowerCallResult()
2080 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), in LowerCallResult()
2355 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
2837 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
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/external/llvm/include/llvm/CodeGen/
DCallingConvLower.h147 unsigned getLocReg() const { assert(isRegLoc()); return Loc; } in getLocReg() function
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1080 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(), in LowerCallResult()
1177 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCCCCallTo()
1338 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerCCCArguments()
1527 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
1532 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp351 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); in LowerReturn()
355 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
396 RVLocs[i].getLocReg(), in LowerCallResult()
530 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
887 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
892 RegInfo.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1385 unsigned SourcePhysReg = VA.getLocReg(); in finishCall()
1599 unsigned RetReg = VA.getLocReg(); in SelectRet()
1619 RetRegs.push_back(VA.getLocReg()); in SelectRet()
DPPCISelLowering.cpp2699 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
4110 VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
4447 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall_32SVR4()
5574 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); in LowerReturn()
5576 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp2981 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); in processCallArgs()
2982 CLI.OutRegs.push_back(VA.getLocReg()); in processCallArgs()
3046 .addReg(RVLocs[0].getLocReg()); in finishCall()
3047 CLI.InRegs.push_back(RVLocs[0].getLocReg()); in finishCall()
3702 unsigned DestReg = VA.getLocReg(); in selectRet()
3740 RetRegs.push_back(VA.getLocReg()); in selectRet()
DAArch64ISelLowering.cpp2138 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments()
2350 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag); in LowerCallResult()
2464 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) in isEligibleForTailCallOptimization()
2711 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); in LowerCall()
2944 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag); in LowerReturn()
2946 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp741 MRI.addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
819 unsigned Reg = VA.getLocReg(); in canUseSiblingCall()
881 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); in LowerCall()
974 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), in LowerCall()
1019 unsigned Reg = VA.getLocReg(); in LowerReturn()
/external/llvm/lib/Target/R600/
DSIISelLowering.cpp542 unsigned Reg = VA.getLocReg(); in LowerFormalArguments()
567 Reg = ArgLocs[ArgIdx++].getLocReg(); in LowerFormalArguments()
DR600ISelLowering.cpp1671 unsigned Reg = MF.addLiveIn(VA.getLocReg(), &AMDGPU::R600_Reg128RegClass); in LowerFormalArguments()