| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUInstrInfo.cpp | 227 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const { in isPredicable() function in AMDGPUInstrInfo
229 return MI->getDesc().isPredicable(); in isPredicable()
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| D | R600InstrInfo.h | 77 bool isPredicable(MachineInstr *MI) const;
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| D | R600InstrInfo.cpp | 360 R600InstrInfo::isPredicable(MachineInstr *MI) const in isPredicable() function in R600InstrInfo
362 return AMDGPUInstrInfo::isPredicable(MI); in isPredicable()
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| D | AMDGPUInstrInfo.h | 121 bool isPredicable(MachineInstr *MI) const;
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 314 bool isPredicable() const { in isPredicable() function
635 if (isPredicable()) { in findFirstPredOperandIdx()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 689 if (!NewMCID.isPredicable()) in ReduceTo2Addr()
693 SkipPred = !NewMCID.isPredicable(); in ReduceTo2Addr()
786 if (!NewMCID.isPredicable()) in ReduceToNarrow()
790 SkipPred = !NewMCID.isPredicable(); in ReduceToNarrow()
844 if (!MCID.isPredicable() && NewMCID.isPredicable()) in ReduceToNarrow()
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| D | ARMBaseInstrInfo.h | 144 bool isPredicable(MachineInstr *MI) const override;
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 140 bool isPredicable; variable
238 bool isPredicable : 1; variable
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| D | CodeGenInstruction.cpp | 29 isPredicable = false; in CGIOperandList()
97 isPredicable = true; in CGIOperandList()
310 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable"); in CodeGenInstruction()
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| D | InstrInfoEmitter.cpp | 496 if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)"; in emitRecord()
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| /external/llvm/lib/Target/R600/ |
| D | AMDGPUInstrInfo.cpp | 253 bool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const { in isPredicable() function in AMDGPUInstrInfo
255 return MI->getDesc().isPredicable(); in isPredicable()
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| D | AMDGPUInstrInfo.h | 130 bool isPredicable(MachineInstr *MI) const override;
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| D | R600InstrInfo.h | 171 bool isPredicable(MachineInstr *MI) const override;
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 154 bool isPredicable(MachineInstr *MI);
741 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { in isPredicable() function in HexagonExpandCondsets
742 if (HII->isPredicated(MI) || !HII->isPredicable(MI)) in isPredicable()
979 if (!DefI || !isPredicable(DefI)) in predicate()
1284 if (!RDef || !HII->isPredicable(RDef)) in coalesceSegments()
1290 if (!RDef || !HII->isPredicable(RDef)) in coalesceSegments()
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| D | HexagonInstrInfo.h | 126 bool isPredicable(MachineInstr *MI) const override;
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| D | HexagonInstrInfo.cpp | 732 bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { in isPredicable() function in HexagonInstrInfo
733 bool isPred = MI->getDesc().isPredicable(); in isPredicable()
879 assert (isPredicable(MI) && "Expected predicable instruction"); in PredicateInstruction()
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| D | HexagonInstrInfoV3.td | 24 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicable = 1,
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| D | HexagonInstrInfoV4.td | 588 let isPredicable = 1 in
834 let isPredicable = 1 in
896 let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
1038 let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
1232 let opNewValue = 2, opExtendable = 1, isExtentSigned = 1, isPredicable = 1 in
1383 let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc, isNVStore = 1,
3244 let isBarrier = 1, isPredicable = 1 in
3263 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
3281 let hasSideEffects = 0, isPredicable = 1, isNVStorable = 1 in
3367 let opExtendable = 0, isPredicable = 1 in
[all …]
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| D | HexagonInstrInfo.td | 216 let isPredicable = 1 in
242 let isPredicable = 1 in
406 let opExtendable = 2, opExtentBits = 16, isPredicable = 1 in
529 let isPredicable = 1 in
580 let isPredicable = 1 in
623 isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
786 let isPredicable = 1, hasSideEffects = 0 in
827 let isPredicable = 1, hasSideEffects = 0 in
1440 isPredicable = 1,
1501 isPredicable = 1, hasSideEffects = 0, InputType = "reg" in
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 916 virtual bool isPredicable(MachineInstr *MI) const { in isPredicable() function
917 return MI->getDesc().isPredicable(); in isPredicable()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.h | 160 bool isPredicable(MachineInstr *MI) const override;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 222 bool isPredicable(MachineInstr *MI) const override;
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.cpp | 167 if (!MI->isPredicable()) in isUnpredicatedTerminator()
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 209 if (!MI->isPredicable()) in isUnpredicatedTerminator()
223 if (!MI->isPredicable()) in PredicateInstruction()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 465 bool isPredicable(QueryType Type = AllInBundle) const {
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