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Searched refs:isReg (Results 1 – 25 of 180) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DMachineOperand.h191 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
194 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
199 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
227 bool isReg() const { return OpKind == MO_Register; } in isReg() function
265 assert(isReg() && "This is not a register operand!"); in getReg()
270 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
275 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
280 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
285 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
290 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
[all …]
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
191 if (Op.isReg()) { in printOperand()
296 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
298 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
301 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
304 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
307 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
310 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); in printAlias()
313 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
[all …]
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp174 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
186 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
199 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
212 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
224 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
237 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
256 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
276 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
292 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
308 assert(MI.getOperand(OpNo+1).isReg()); in getSPE2DisEncoding()
[all …]
/external/llvm/lib/CodeGen/
DMachineInstr.cpp92 assert(isReg() && "Wrong MachineOperand accessor"); in setIsDef()
112 if (!isReg() || !isOnRegUseList()) in removeRegFromUses()
127 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToImmediate()
136 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToFPImmediate()
157 bool WasReg = isReg(); in ChangeToRegister()
640 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
649 if (MO.isReg()) in AddRegOperandsToUseLists()
696 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
698 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) { in addOperand()
743 if (NewMO->isReg()) { in addOperand()
[all …]
DLivePhysRegs.cpp40 if (O->isReg()) { in stepBackward()
53 if (!O->isReg() || !O->readsReg() || O->isUndef()) in stepBackward()
70 if (O->isReg()) { in stepForward()
DDeadMachineInstructionElim.cpp74 if (MO.isReg() && MO.isDef()) { in isDead()
144 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
163 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
DMachineLICM.cpp450 if (!MO.isReg()) in ProcessMI()
557 if (!MO.isReg()) in HoistRegionPostRA()
586 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA()
616 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns()
804 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) in SinkIntoLoop()
882 if (!MO.isReg() || MO.isImplicit()) in calcRegisterCost()
966 if (!MO.isReg()) in IsLoopInvariantInst()
1016 if (!MO->isReg() || !MO->isDef()) in HasLoopPHIUse()
1059 if (!MO.isReg() || !MO.isUse()) in HasHighOperandLatency()
1088 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
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DExpandPostRAPseudos.cpp74 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs()
82 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
84 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
DMachineCSE.cpp127 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
193 if (!MO.isReg() || !MO.getReg()) in isPhysDefTriviallyDead()
225 if (!MO.isReg() || MO.isDef()) in hasLivePhysRegDefUses()
244 if (!MO.isReg() || !MO.isDef()) in hasLivePhysRegDefUses()
320 if (!MO.isReg() || !MO.isDef()) in PhysRegDefsReach()
403 if (MO.isReg() && MO.isUse() && in isProfitableToCSE()
538 if (!MO.isReg() || !MO.isDef()) in ProcessBlock()
/external/llvm/lib/Target/R600/
DSIFoldOperands.cpp66 assert(FoldOp->isReg()); in FoldCandidate()
110 assert(Old.isReg()); in updateOperand()
182 if (!FoldingImm && !OpToFold.isReg()) in runOnMachineFunction()
193 if (OpToFold.isReg() && in runOnMachineFunction()
207 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in runOnMachineFunction()
278 assert(Fold.OpToFold && Fold.OpToFold->isReg()); in runOnMachineFunction()
DSIInstrInfo.cpp719 assert(SrcOp.isReg()); in expandPostRAPseudo()
765 if (!Src0.isReg()) in commuteInstruction()
782 if (!Src1.isReg()) { in commuteInstruction()
844 if (!MI->getOperand(Src0Idx).isReg()) in findCommutedOpIndices()
851 if (!MI->getOperand(Src1Idx).isReg()) in findCommutedOpIndices()
924 if (Src0->isReg() && Src0->getReg() == Reg) { in FoldImmediate()
925 if (!Src1->isReg() || in FoldImmediate()
926 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
929 if (!Src2->isReg() || in FoldImmediate()
930 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))) in FoldImmediate()
[all …]
DSIInsertWaits.cpp157 assert(Op.isReg() && "First LGKM operand must be a register!"); in getHwCounts()
178 if (!Op.isReg()) in isOpRelevant()
220 if (I->isReg() && I->isUse()) in isOpRelevant()
229 if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg())) in getRegInterval()
434 if (Op.isReg() && Op.isDef() && Op.getReg() == AMDGPU::M0) in handleSendMsg()
/external/llvm/lib/Target/Hexagon/
DHexagonHardwareLoops.cpp250 bool isReg() const { return Kind == CV_Register; } in isReg() function in __anonfb58bf460111::CountValue
254 assert(isReg() && "Wrong CountValue accessor"); in getReg()
258 assert(isReg() && "Wrong CountValue accessor"); in getSubReg()
267 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } in print()
522 if (Op1.isReg()) { in getLoopTripCount()
559 if (InitialValue->isReg()) { in getLoopTripCount()
586 if (InitialValue->isReg()) { in getLoopTripCount()
593 if (EndValue->isReg()) { in getLoopTripCount()
619 if (Start->isReg()) { in computeCount()
624 if (End->isReg()) { in computeCount()
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DHexagonExpandCondsets.cpp268 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) in makeDefined()
300 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg) in makeUndead()
328 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg) in shrinkToUses()
357 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) in updateKillFlags()
428 if (Op.isReg() && Op.isDef()) in addInstrToLiveness()
505 if (!Op.isReg() || !Op.isUse() || Op.isImplicit() || Op.isUndef()) in addInstrToLiveness()
544 if (!Op.isReg() || !Op.isDef()) in removeInstrFromLiveness()
622 if (!Op.isReg() || !Op.isUse()) in removeInstrFromLiveness()
643 if (SO.isReg()) { in getCondTfrOpcode()
749 if (!Op.isReg() || !Op.isDef()) in isPredicable()
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DHexagonNewValueJump.cpp150 if (II->getOperand(i).isReg() && in INITIALIZE_PASS_DEPENDENCY()
466 MI->getOperand(0).isReg() && in runOnMachineFunction()
474 isSecondOpReg = MI->getOperand(2).isReg(); in runOnMachineFunction()
508 if (MI->getOperand(0).isReg() && in runOnMachineFunction()
565 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
572 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
627 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction()
630 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
DHexagonCopyToCombine.cpp119 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isReg()); in isCombinableInstType()
132 assert(Op0.isReg()); in isCombinableInstType()
150 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isGlobal()); in isCombinableInstType()
210 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill()) in removeKillInfo()
367 if (!Op.isReg() || !Op.isUse() || !Op.getReg()) in findPotentialNewifiableTFRs()
397 if (!Op.isReg() || !Op.isDef() || !Op.getReg()) in findPotentialNewifiableTFRs()
536 bool IsHiReg = HiOperand.isReg(); in combine()
537 bool IsLoReg = LoOperand.isReg(); in combine()
DHexagonVLIWPacketizer.cpp354 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) { in IsCallDependent()
480 if (MI->getOperand(opNum).isReg() && in GetPostIncrementOperand()
486 if (MI->getOperand(opNum).isReg() && in GetPostIncrementOperand()
495 assert(MI->getOperand(1).isReg() && in GetPostIncrementOperand()
501 assert(MI->getOperand(0).isReg() && in GetPostIncrementOperand()
544 if (GetStoreValueOperand(MI).isReg() && in CanPromoteToNewValueStore()
608 if ( PacketMI->getOperand(opNum).isReg()) in CanPromoteToNewValueStore()
620 if ( MI->getOperand(opNum).isReg()) in CanPromoteToNewValueStore()
674 if (MI->getOperand(opNum).isReg() && in CanPromoteToNewValueStore()
688 GetStoreValueOperand(MI).isReg() && in CanPromoteToNewValueStore()
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DHexagonAsmPrinter.cpp131 if (!MI->getOperand(OpNo).isReg() || in PrintAsmOperand()
133 !MI->getOperand(OpNo+1).isReg()) in PrintAsmOperand()
160 if (Base.isReg()) in PrintAsmMemoryOperand()
/external/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcMCCodeEmitter.cpp117 if (MO.isReg()) in getMachineOpValue()
144 if (MO.isReg() || MO.isImm()) in getCallTargetOpValue()
179 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
192 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue()
204 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
/external/llvm/lib/Target/Sparc/InstPrinter/
DSparcInstPrinter.cpp62 if (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
86 || (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
112 if (MO.isReg()) { in printOperand()
139 if (MO.isReg() && MO.getReg() == SP::G0) in printMemOperand()
/external/llvm/lib/Target/R600/AsmParser/
DAMDGPUAsmParser.cpp105 if (isReg()) in addRegOrImmOperands()
166 bool isReg() const override { in isReg() function in __anondcc3d2080111::AMDGPUOperand
175 assert(isReg()); in setModifiers()
184 return isReg() || isImm(); in isRegOrImm()
192 return isInlineImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID)); in isSCSrc32()
196 return isImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID)); in isSSrc32()
201 (isReg() && isRegClass(AMDGPU::SReg_64RegClassID)); in isSSrc64()
205 return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID)); in isVCSrc32()
209 return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID)); in isVCSrc64()
213 return isImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID)); in isVSrc32()
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/external/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp191 bool isReg() const override { in isReg() function in __anon920606c00111::SystemZOperand
194 bool isReg(RegisterKind RegKind) const { in isReg() function in __anon920606c00111::SystemZOperand
294 bool isGR32() const { return isReg(GR32Reg); } in isGR32()
295 bool isGRH32() const { return isReg(GRH32Reg); } in isGRH32()
297 bool isGR64() const { return isReg(GR64Reg); } in isGR64()
298 bool isGR128() const { return isReg(GR128Reg); } in isGR128()
299 bool isADDR32() const { return isReg(ADDR32Reg); } in isADDR32()
300 bool isADDR64() const { return isReg(ADDR64Reg); } in isADDR64()
302 bool isFP32() const { return isReg(FP32Reg); } in isFP32()
303 bool isFP64() const { return isReg(FP64Reg); } in isFP64()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp141 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) in getDebugValueLocation()
240 assert(MO.isReg() && "Should only get here with a register!"); in printAsmRegInClass()
270 if (MO.isReg()) in PrintAsmOperand()
284 if (MO.isReg()) { in PrintAsmOperand()
314 if (MO.isReg()) { in PrintAsmOperand()
340 assert(MO.isReg() && "unexpected inline asm memory operand"); in PrintAsmMemoryOperand()
355 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); in PrintDebugValueComment()
/external/llvm/include/llvm/MC/
DMCInst.h56 bool isReg() const { return Kind == kRegister; } in isReg() function
64 assert(isReg() && "This is not a register operand!"); in getReg()
70 assert(isReg() && "This is not a register operand!"); in setReg()
/external/llvm/lib/Target/BPF/InstPrinter/
DBPFInstPrinter.cpp54 if (Op.isReg()) { in printOperand()
75 assert(RegOp.isReg() && "Register operand not a register"); in printMemOperand()

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