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Searched refs:no_shift (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h25 default: return ARM_AM::no_shift; in getShiftOpcForNode()
DARMFastISel.cpp2637 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, in ARMEmitIntExt()
2638 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, in ARMEmitIntExt()
2639 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, in ARMEmitIntExt()
2640 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, in ARMEmitIntExt()
2641 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, in ARMEmitIntExt()
2642 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } in ARMEmitIntExt()
2647 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2648 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, in ARMEmitIntExt()
2649 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, in ARMEmitIntExt()
2650 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, in ARMEmitIntExt()
[all …]
DARMISelDAGToDAG.cpp478 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectImmShifterOperand()
502 if (ShOpcVal == ARM_AM::no_shift) return false; in SelectRegShifterOperand()
615 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
625 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
628 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
633 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && in SelectLdStSOReg()
637 if (ShOpcVal != ARM_AM::no_shift) { in SelectLdStSOReg()
648 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
651 ShOpcVal = ARM_AM::no_shift; in SelectLdStSOReg()
705 ARM_AM::no_shift), in SelectAddrMode2Worker()
[all …]
DARMLoadStoreOptimizer.cpp1342 int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
1360 int Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift); in MergeBaseUpdateLoadStore()
DARMFrameLowering.cpp1080 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); in emitPopInst()
DARMISelLowering.cpp10254 if (ShOpcVal != ARM_AM::no_shift) { in getARMIndexedAddressParts()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h28 no_shift = 0, enumerator
DARMMCCodeEmitter.cpp207 case ARM_AM::no_shift: in getShiftOp()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1119 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; in isPostIdxReg()
1226 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1240 return PostIdxReg.ShiftTy == ARM_AM::no_shift; in isAM3Offset()
1265 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1286 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1296 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
2126 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAddrMode2Operands()
2147 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); in addAM2OffsetImmOperands()
2890 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) in print()
3063 .Default(ARM_AM::no_shift); in tryParseShiftRegister()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp44 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) in printRegImmShift()