Home
last modified time | relevance | path

Searched refs:rd (Results 1 – 25 of 322) sorted by relevance

12345678910>>...13

/external/fio/engines/
Drdma.c121 struct rdmaio_data *rd = td->io_ops->data; in client_recv() local
123 if (wc->byte_len != sizeof(rd->recv_buf)) { in client_recv()
129 if ((rd->rdma_protocol == FIO_RDMA_MEM_WRITE) || in client_recv()
130 (rd->rdma_protocol == FIO_RDMA_MEM_READ)) { in client_recv()
134 rd->rmt_nr = ntohl(rd->recv_buf.nr); in client_recv()
136 for (i = 0; i < rd->rmt_nr; i++) { in client_recv()
137 rd->rmt_us[i].buf = ntohll(rd->recv_buf.rmt_us[i].buf); in client_recv()
138 rd->rmt_us[i].rkey = ntohl(rd->recv_buf.rmt_us[i].rkey); in client_recv()
139 rd->rmt_us[i].size = ntohl(rd->recv_buf.rmt_us[i].size); in client_recv()
143 " len %d from peer\n", rd->rmt_us[i].rkey, in client_recv()
[all …]
/external/valgrind/none/tests/mips64/
Dcvm_atomic.stdout.exp-LE1 baddu $t3, $t1, $t2 :: rd 0x4, rs 0x42b0c0a28677b502, rt 0x42b0c0a28677b502
2 baddu $t3, $t1, $t2 :: rd 0xa2, rs 0x42b0c0a28677b502, rt 0x9e705cc51ad8dca0
3 baddu $t3, $t1, $t2 :: rd 0x82, rs 0x42b0c0a28677b502, rt 0x47f505569a08a180
4 baddu $t3, $t1, $t2 :: rd 0x99, rs 0x42b0c0a28677b502, rt 0x94ff52fc81afa797
5 baddu $t3, $t1, $t2 :: rd 0xc7, rs 0x42b0c0a28677b502, rt 0x556b3ecaccf17ac5
6 baddu $t3, $t1, $t2 :: rd 0x68, rs 0x42b0c0a28677b502, rt 0x3c2cd9a9cda20766
7 baddu $t3, $t1, $t2 :: rd 0x38, rs 0x42b0c0a28677b502, rt 0xd0d070db710cd036
8 baddu $t3, $t1, $t2 :: rd 0xa9, rs 0x42b0c0a28677b502, rt 0x2f39454412d6e4a7
9 baddu $t3, $t1, $t2 :: rd 0x16, rs 0x42b0c0a28677b502, rt 0xed5005cbc8b0a214
10 baddu $t3, $t1, $t2 :: rd 0x42, rs 0x42b0c0a28677b502, rt 0x87750a04ad765040
[all …]
Dcvm_ins.stdout.exp514 sne $t1, $t2 ,$t3 :: rd 0x0 rs 0x0, rt 0x0
515 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x130476dc
516 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x2608edb8
517 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x350c9b64
518 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x4c11db70
519 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x5f15adac
520 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x6a1936c8
521 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x791d4014
522 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x9823b6e0
523 sne $t1, $t2 ,$t3 :: rd 0x1 rs 0x0, rt 0x8b27c03c
[all …]
Darithmetic_instruction.stdout.exp-mips64r21 add $t0, $t1, $t2 :: rd 0xffffffffb1f740b4, rs 0x0, rt 0xffffffffb1f740b4
2 add $t0, $t1, $t2 :: rd 0xffffffffb5365d03, rs 0x0, rt 0xffffffffb5365d03
3 add $t0, $t1, $t2 :: rd 0xffffffffc1f7b748, rs 0x9823b6e, rt 0xffffffffb8757bda
4 add $t0, $t1, $t2 :: rd 0xffffffffc9f78d46, rs 0xd4326d9, rt 0xffffffffbcb4666d
5 add $t0, $t1, $t2 :: rd 0xffffffffb5f7ad44, rs 0x130476dc, rt 0xffffffffa2f33668
6 add $t0, $t1, $t2 :: rd 0xffffffffbdf7974a, rs 0x17c56b6b, rt 0xffffffffa6322bdf
7 add $t0, $t1, $t2 :: rd 0xffffffffc5f75ab8, rs 0x1a864db2, rt 0xffffffffab710d06
8 add $t0, $t1, $t2 :: rd 0xffffffffcdf760b6, rs 0x1e475005, rt 0xffffffffafb010b1
9 add $t0, $t1, $t2 :: rd 0xffffffffbe089ac4, rs 0x2608edb8, rt 0xffffffff97ffad0c
10 add $t0, $t1, $t2 :: rd 0xffffffffb608a0ca, rs 0x22c9f00f, rt 0xffffffff933eb0bb
[all …]
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h46 void MacroAssembler::And(const Register& rd, in And() argument
50 DCHECK(!rd.IsZero()); in And()
51 LogicalMacro(rd, rn, operand, AND); in And()
55 void MacroAssembler::Ands(const Register& rd, in Ands() argument
59 DCHECK(!rd.IsZero()); in Ands()
60 LogicalMacro(rd, rn, operand, ANDS); in Ands()
71 void MacroAssembler::Bic(const Register& rd, in Bic() argument
75 DCHECK(!rd.IsZero()); in Bic()
76 LogicalMacro(rd, rn, operand, BIC); in Bic()
80 void MacroAssembler::Bics(const Register& rd, in Bics() argument
[all …]
Dassembler-arm64.cc1073 void Assembler::adr(const Register& rd, int imm21) { in adr() argument
1074 DCHECK(rd.Is64Bits()); in adr()
1075 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
1079 void Assembler::adr(const Register& rd, Label* label) { in adr() argument
1080 adr(rd, LinkAndGetByteOffsetTo(label)); in adr()
1084 void Assembler::add(const Register& rd, in add() argument
1087 AddSub(rd, rn, operand, LeaveFlags, ADD); in add()
1091 void Assembler::adds(const Register& rd, in adds() argument
1094 AddSub(rd, rn, operand, SetFlags, ADD); in adds()
1105 void Assembler::sub(const Register& rd, in sub() argument
[all …]
Dassembler-arm64.h1081 void adr(const Register& rd, Label* label);
1082 void adr(const Register& rd, int imm21);
1086 void add(const Register& rd,
1091 void adds(const Register& rd,
1099 void sub(const Register& rd,
1104 void subs(const Register& rd,
1112 void neg(const Register& rd,
1116 void negs(const Register& rd,
1120 void adc(const Register& rd,
1125 void adcs(const Register& rd,
[all …]
/external/libvpx/libvpx/vp9/encoder/
Dvp9_rd.c146 static void set_block_thresholds(const VP9_COMMON *cm, RD_OPT *rd) { in set_block_thresholds() argument
164 rd->threshes[segment_id][bsize][i] = in set_block_thresholds()
165 rd->thresh_mult[i] < thresh_max in set_block_thresholds()
166 ? rd->thresh_mult[i] * t / 4 in set_block_thresholds()
170 rd->threshes[segment_id][bsize][i] = in set_block_thresholds()
171 rd->thresh_mult_sub8x8[i] < thresh_max in set_block_thresholds()
172 ? rd->thresh_mult_sub8x8[i] * t / 4 in set_block_thresholds()
182 RD_OPT *const rd = &cpi->rd; in vp9_initialize_rd_consts() local
187 rd->RDDIV = RDDIV_BITS; // In bits (to multiply D by 128). in vp9_initialize_rd_consts()
188 rd->RDMULT = vp9_compute_rd_mult(cpi, cm->base_qindex + cm->y_dc_delta_q); in vp9_initialize_rd_consts()
[all …]
/external/valgrind/none/tests/mips32/
DMIPS32int.stdout.exp-mips32-BE2 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
3 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
4 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
5 add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
6 add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
7 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
8 add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
9 add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
10 add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
11 add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
[all …]
DMIPS32int.stdout.exp-mips32-LE2 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
3 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
4 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
5 add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
6 add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
7 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
8 add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
9 add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
10 add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
11 add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
[all …]
DMIPS32int.stdout.exp-mips32r2-LE2 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
3 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
4 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
5 add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
6 add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
7 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
8 add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
9 add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
10 add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
11 add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
[all …]
DMIPS32int.stdout.exp-mips32r2-BE2 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000000, rt 0x00000000
3 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000000, rt 0x00000001
4 add $t0, $t1, $t2 :: rd 0x00000001 rs 0x00000001, rt 0x00000000
5 add $t0, $t1, $t2 :: rd 0x00000002 rs 0x00000001, rt 0x00000001
6 add $t0, $t1, $t2 :: rd 0xffffffff rs 0x00000000, rt 0xffffffff
7 add $t0, $t1, $t2 :: rd 0x00000000 rs 0x00000001, rt 0xffffffff
8 add $t0, $t1, $t2 :: rd 0x80000000 rs 0x80000000, rt 0x00000000
9 add $t0, $t1, $t2 :: rd 0x5859704f rs 0x31415927, rt 0x27181728
10 add $t0, $t1, $t2 :: rd 0xc859704f rs 0x31415927, rt 0x97181728
11 add $t0, $t1, $t2 :: rd 0xffffffff rs 0xffffffff, rt 0x00000000
[all …]
/external/valgrind/none/tests/arm/
Dv6intARM.stdout.exp2 mov r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
3 cpy r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
6 movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 0, cpsr 0x00000000
7 movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 0, cpsr 0x40000000 Z
8 movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 0, cpsr 0x80000000 N
11 movs r0, r1 :: rd 0x00000001 rm 0x00000001, carryin 1, cpsr 0x20000000 C
12 movs r0, r1 :: rd 0x00000000 rm 0x00000000, carryin 1, cpsr 0x60000000 ZC
13 movs r0, r1 :: rd 0x80000000 rm 0x80000000, carryin 1, cpsr 0xa0000000 N C
17 mvn r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x00000000
18 mvns r0, r1 :: rd 0xfffffffe rm 0x00000001, carryin 0, cpsr 0x80000000 N
[all …]
Dv6media.stdout.exp2 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[…
3 mul r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 ge[…
4 mul r0, r1, r2 :: rd 0x00000000 rm 0x00000000, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[…
5 mul r0, r1, r2 :: rd 0x00000001 rm 0xffffffff, rn 0xffffffff, carryin 0, cpsr 0x00000000 ge[…
6 mul r0, r1, r2 :: rd 0x00000001 rm 0x7fffffff, rn 0x7fffffff, carryin 0, cpsr 0x00000000 ge[…
7 mul r0, r1, r2 :: rd 0xfffe0001 rm 0x0000ffff, rn 0x0000ffff, carryin 0, cpsr 0x00000000 ge[…
9 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x…
10 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0xffffffff, rn 0x00000000 rs 0x00000001, carryin 0, cpsr 0x…
11 mla r0, r1, r2, r3 :: rd 0x00000001 rm 0x00000000, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x…
12 mla r0, r1, r2, r3 :: rd 0x00000002 rm 0xffffffff, rn 0xffffffff rs 0x00000001, carryin 0, cpsr 0x…
[all …]
/external/valgrind/none/tests/arm64/
Dinteger.stdout.exp2 add x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000…
3 add w3, w4, w5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000…
4 adc x3, x4, x5 :: rd 0000000000004abe rm 0000000000003039, rn 0000000000001a85, cin 0, nzcv 0000000…
5 adc x3, x4, x5 :: rd 0000000000004abf rm 0000000000003039, rn 0000000000001a85, cin 1, nzcv 2000000…
6 adc x3, x4, x5 :: rd ffffffffffffffff rm 0000000000000000, rn ffffffffffffffff, cin 0, nzcv 0000000…
7 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn ffffffffffffffff, cin 1, nzcv 2000000…
8 adc x3, x4, x5 :: rd 5859704f00000000 rm 3141592700000000, rn 2718172800000000, cin 0, nzcv 0000000…
9 adc x3, x4, x5 :: rd 5859704f00000001 rm 3141592700000000, rn 2718172800000000, cin 1, nzcv 2000000…
10 adc x3, x4, x5 :: rd 0000000000000000 rm 0000000000000000, rn 0000000000000000, cin 0, nzcv 0000000…
11 adc x3, x4, x5 :: rd 0000000000000001 rm 0000000000000000, rn 0000000000000000, cin 1, nzcv 2000000…
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrVIS.td21 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
22 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
27 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
28 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
31 let rd = 0, rs1 = 0, rs2 = 0 in
35 // For VIS Instructions with only rs1, rd operands.
39 (outs RC:$rd), (ins RC:$rs1),
40 !strconcat(OpcStr, " $rs1, $rd"), []>;
42 // For VIS Instructions with only rs2, rd operands.
46 (outs RC:$rd), (ins RC:$rs2),
[all …]
DSparcInstrInfo.td252 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
253 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
254 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
256 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
257 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
258 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
265 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
266 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
268 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
269 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
[all …]
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc2220 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing1Source() local
2241 case FSQRT_d: fsqrt(vform, rd, rn); return; in VisitFPDataProcessing1Source()
2260 frint(vform, rd, rn, fpcr_rounding, inexact_exception); in VisitFPDataProcessing1Source()
2268 SimVRegister& rd = vreg(instr->Rd()); in VisitFPDataProcessing2Source() local
2274 case FADD_d: fadd(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
2276 case FSUB_d: fsub(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
2278 case FMUL_d: fmul(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
2280 case FNMUL_d: fnmul(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
2282 case FDIV_d: fdiv(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
2284 case FMAX_d: fmax(vform, rd, rn, rm); break; in VisitFPDataProcessing2Source()
[all …]
Dmacro-assembler-a64.h595 const Register &rd,
603 void And(const Register& rd,
606 void Ands(const Register& rd,
609 void Bic(const Register& rd,
612 void Bics(const Register& rd,
615 void Orr(const Register& rd,
618 void Orn(const Register& rd,
621 void Eor(const Register& rd,
624 void Eon(const Register& rd,
628 void LogicalMacro(const Register& rd,
[all …]
/external/icu/icu4c/source/test/cintltst/
Duregiontest.c360 const KnownRegion * rd; in TestKnownRegions() local
361 for (rd = knownRegions; rd->code != NULL ; rd++ ) { in TestKnownRegions()
363 const URegion *r = uregion_getRegionFromCode(rd->code, &status); in TestKnownRegions()
366 int32_t e = rd->numeric; in TestKnownRegions()
370 if (uregion_getType(r) != rd->type) { in TestKnownRegions()
371 …Expected region %s to be of type %d. Got: %d\n", uregion_getRegionCode(r), rd->type, uregion_getTy… in TestKnownRegions()
381 log_data_err("ERROR: Known region %s was not recognized.\n", rd->code); in TestKnownRegions()
387 const KnownRegion * rd; in TestGetContainedRegions() local
388 for (rd = knownRegions; rd->code != NULL ; rd++ ) { in TestGetContainedRegions()
390 const URegion *r = uregion_getRegionFromCode(rd->code, &status); in TestGetContainedRegions()
[all …]
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/test/util/
DRegionTest.java339 for (String [] rd : knownRegions ) { in TestKnownRegions()
341 Region r = Region.getInstance(rd[0]); in TestKnownRegions()
343 int e = Integer.valueOf(rd[1]).intValue(); in TestKnownRegions()
347 if (r.getType() != Region.RegionType.valueOf(rd[3])) { in TestKnownRegions()
348 …errln("Expected region " + r.toString() + " to be of type " + rd[3] + ". Got:" + r.getType().toStr… in TestKnownRegions()
350 int nc = Integer.valueOf(rd[1]).intValue(); in TestKnownRegions()
358 errln("Known region " + rd[0] + " was not recognized."); in TestKnownRegions()
436 for (String [] rd : knownRegions ) { in TestGetContainedRegions()
438 Region r = Region.getInstance(rd[0]); in TestGetContainedRegions()
450 errln("Known region " + rd[0] + " was not recognized."); in TestGetContainedRegions()
[all …]
/external/valgrind/VEX/priv/
Dguest_tilegx_toIR.c278 ULong cins, opcode = -1, rd, ra, rb, imm = 0; in disInstr_TILEGX_WRK() local
409 rd = ra = rb = -1; in disInstr_TILEGX_WRK()
422 if (rd == -1) in disInstr_TILEGX_WRK()
423 rd = decoded[n].operand_values[opi]; in disInstr_TILEGX_WRK()
472 MARK_REG_WB(rd, t2); in disInstr_TILEGX_WRK()
477 MARK_REG_WB(rd, t2); in disInstr_TILEGX_WRK()
482 MARK_REG_WB(rd, t2); in disInstr_TILEGX_WRK()
521 MARK_REG_WB(rd, t2); in disInstr_TILEGX_WRK()
527 MARK_REG_WB(rd, t2); in disInstr_TILEGX_WRK()
533 MARK_REG_WB(rd, t2); in disInstr_TILEGX_WRK()
[all …]
/external/llvm/test/CodeGen/NVPTX/
Darithmetic-int.ll12 ; CHECK: add.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
19 ; CHECK: sub.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
26 ; CHECK: mul.lo.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
33 ; CHECK: div.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
40 ; CHECK: div.u64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
47 ; CHECK: rem.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
54 ; CHECK: rem.u64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
61 ; CHECK: and.b64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
68 ; CHECK: or.b64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
75 ; CHECK: xor.b64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
[all …]
Dld-addrspace.ll9 ; PTX64: ld.global.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
18 ; PTX64: ld.shared.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
27 ; PTX64: ld.local.u8 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
37 ; PTX64: ld.global.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
46 ; PTX64: ld.shared.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
55 ; PTX64: ld.local.u16 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
65 ; PTX64: ld.global.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
74 ; PTX64: ld.shared.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
83 ; PTX64: ld.local.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
91 ; PTX32: ld.global.u64 %rd{{[0-9]+}}, [%r{{[0-9]+}}]
[all …]
/external/v8/src/mips64/
Dassembler-mips64.cc350 Register rd; in GetRdReg() local
351 rd.code_ = (instr & kRdFieldMask) >> kRdShift; in GetRdReg()
352 return rd; in GetRdReg()
564 uint32_t rd = GetRd(instr); in IsNop() local
574 rd == static_cast<uint32_t>(ToNumber(zero_reg)) && in IsNop()
853 Register rd, in GenInstrRegister() argument
856 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); in GenInstrRegister()
858 | (rd.code() << kRdShift) | (sa << kSaShift) | func; in GenInstrRegister()
1411 void Assembler::jalr(Register rs, Register rd) { in jalr() argument
1414 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr()
[all …]

12345678910>>...13