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Searched refs:setlt (Results 1 – 23 of 23) sorted by relevance

/external/clang/test/CodeGen/
DBasicInstrs.c19 _Bool setlt(int X, int Y) { in setlt() function
/external/llvm/test/Transforms/InstCombine/
Dsetcc-strength-reduce.ll2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
Dcast.ll141 ; %X = setlt sbyte %c, 0 ; setgt %A, 127
/external/llvm/test/Transforms/LoopStrengthReduce/
Ddont-hoist-simple-loop-constants.ll4 ; The setlt wants to use a value that is incremented one more than the dominant
/external/llvm/test/CodeGen/PowerPC/
Dppc-vaarg-agg.ll44 ; with an error like: Cannot select: ch = setlt [ID=6]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoVector.td312 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, i1>;
313 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, v8i1>;
314 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, i1>;
315 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, v4i1>;
316 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, i1>;
317 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, v2i1>;
DHexagonSelectCCInfo.td111 // setlt-64 -> setgt-64.
DHexagonInstrInfoV5.td494 def: Pat<(i1 (setlt F32:$src1, F32:$src2)),
496 def: Pat<(i1 (setlt F32:$src1, fpimm:$src2)),
498 def: Pat<(i1 (setlt F64:$src1, F64:$src2)),
500 def: Pat<(i1 (setlt F64:$src1, fpimm:$src2)),
DHexagonInstrInfoV3.td143 defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>;
DHexagonInstrInfo.td282 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones
296 def: T_cmp32_rr_pat<C2_cmpgt, RevCmp<setlt>, i1>;
1201 defm: MinMax_pats<setlt, A2_min, A2_max>;
1238 def: T_cmp64_rr_pat<C2_cmpgtp, RevCmp<setlt>>;
4029 def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)),
4966 def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset),
5041 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
DHexagonInstrInfoV4.td3166 def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td112 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
136 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
219 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
477 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
DMips16InstrInfo.td1454 // bcond-setgt (do we need to have this pair of setlt, setgt??)
1477 // bcond-setlt
1480 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
1485 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
1638 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)),
1774 // x > (k - 1) and then reverses the operands to use setlt. So this pattern
1808 // setlt
1810 def: SetCC_R16<setlt, SltCCRxRy16>;
1812 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
DMicroMipsInstrInfo.td629 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
652 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>;
813 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
DMipsInstrInfo.td1126 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1153 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1306 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1308 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1817 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
DMips32r6InstrInfo.td759 def : MipsPat<(setlt f32:$lhs, f32:$rhs), (CMP_LT_S f32:$lhs, f32:$rhs)>,
779 def : MipsPat<(setlt f64:$lhs, f64:$rhs), (CMP_LT_D f64:$lhs, f64:$rhs)>,
/external/clang/www/demo/
Dindex.cgi99 …$input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|ca…
/external/llvm/test/CodeGen/Mips/
Dfcmp.ll737 ; The optimizers sometimes produce setlt instead of setolt/setult.
781 ; The optimizers sometimes produce setlt instead of setolt/setult.
Dcmov.ll235 ; (movz t, (setlt a, N + 1), f)
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td1245 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1296 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1303 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
/external/llvm/lib/Target/
DREADME.txt41 Shrink: (setlt (loadi32 P), 0) -> (setlt (loadi8 Phi), 0)
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td908 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td1575 defm : ISET_FORMAT_SIGNED<setlt, CmpLT>;
1672 defm FSetLT : FSET_FORMAT<setlt, CmpLT, CmpLT_FTZ>;