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/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_tgsi_aos.c460 LLVMValueRef src0, src1, src2; in lp_emit_instruction_aos() local
484 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
485 dst0 = lp_build_floor(&bld->bld_base.base, src0); in lp_emit_instruction_aos()
497 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
498 dst0 = lp_build_rcp(&bld->bld_base.base, src0); in lp_emit_instruction_aos()
503 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
504 tmp0 = lp_build_emit_llvm_unary(&bld->bld_base, TGSI_OPCODE_ABS, src0); in lp_emit_instruction_aos()
515 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
517 dst0 = lp_build_mul(&bld->bld_base.base, src0, src1); in lp_emit_instruction_aos()
521 src0 = lp_build_emit_fetch(&bld->bld_base, inst, 0, LP_CHAN_ALL); in lp_emit_instruction_aos()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DR600Instructions.td92 (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops),
93 !strconcat(opName, " $dst, $src0, $src1"),
102 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops),
103 !strconcat(opName, " $dst, $src0, $src1, $src2"),
113 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
114 "PRED $dst, $src0, $src1",
117 let DisableEncoding = "$src0";
149 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
150 !strconcat(opName, "$dst, $src0, $src1, $src2"),
243 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
[all …]
DAMDGPUInstructions.td98 (ins rc:$src0),
99 "CLAMP $dst, $src0",
100 [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
105 (ins rc:$src0),
106 "FABS $dst, $src0",
107 [(set rc:$dst, (fabs rc:$src0))]
112 (ins rc:$src0),
113 "FNEG $dst, $src0",
114 [(set rc:$dst, (fneg rc:$src0))]
124 (int_AMDGPU_pow rc:$src0, rc:$src1),
[all …]
DSIInstrFormats.td26 …: VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2, i32imm:$s…
29 …: VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, AllReg_64:$src1, AllReg_64:$src2, i32imm:$s…
33 : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
36 : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
39 : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
42 : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
45 : SOP2 <op, (outs VCCReg:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
50 op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
73 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
95 : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
[all …]
DSIInstructions.td83 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1),
85 [(set SCCReg:$dst, (setcc SReg_32:$src0, imm:$src1, SETEQ))]
111 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LT))]
114 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_EQ))]
117 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_LE))]
120 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GT))]
123 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))]
126 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_GE))]
135 [(set VCCReg:$dst, (setcc (f32 AllReg_32:$src0), VReg_32:$src1, COND_NE))]
254 [(set VCCReg:$dst, (setcc (i32 AllReg_32:$src0), VReg_32:$src1, SETEQ))]
[all …]
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_exec.c114 const union tgsi_exec_channel *src0, in micro_clamp() argument
118 …dst->f[0] = src0->f[0] < src1->f[0] ? src1->f[0] : src0->f[0] > src2->f[0] ? src2->f[0] : src0->f[… in micro_clamp()
119 …dst->f[1] = src0->f[1] < src1->f[1] ? src1->f[1] : src0->f[1] > src2->f[1] ? src2->f[1] : src0->f[… in micro_clamp()
120 …dst->f[2] = src0->f[2] < src1->f[2] ? src1->f[2] : src0->f[2] > src2->f[2] ? src2->f[2] : src0->f[… in micro_clamp()
121 …dst->f[3] = src0->f[3] < src1->f[3] ? src1->f[3] : src0->f[3] > src2->f[3] ? src2->f[3] : src0->f[… in micro_clamp()
126 const union tgsi_exec_channel *src0, in micro_cmp() argument
130 dst->f[0] = src0->f[0] < 0.0f ? src1->f[0] : src2->f[0]; in micro_cmp()
131 dst->f[1] = src0->f[1] < 0.0f ? src1->f[1] : src2->f[1]; in micro_cmp()
132 dst->f[2] = src0->f[2] < 0.0f ? src1->f[2] : src2->f[2]; in micro_cmp()
133 dst->f[3] = src0->f[3] < 0.0f ? src1->f[3] : src2->f[3]; in micro_cmp()
[all …]
/external/mesa3d/src/gallium/docs/source/
Dtgsi.rst15 registers, called *src0* through *src2*, or simply *src* if there is only
122 dst.x = src0.x \times src1.x
124 dst.y = src0.y \times src1.y
126 dst.z = src0.z \times src1.z
128 dst.w = src0.w \times src1.w
135 dst.x = src0.x + src1.x
137 dst.y = src0.y + src1.y
139 dst.z = src0.z + src1.z
141 dst.w = src0.w + src1.w
150 dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z
[all …]
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_vec4.h163 src_reg src0 = src_reg(),
336 vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
339 src_reg src0, src_reg src1);
342 src_reg src0, src_reg src1, src_reg src2);
347 vec4_instruction *MOV(dst_reg dst, src_reg src0);
348 vec4_instruction *NOT(dst_reg dst, src_reg src0);
349 vec4_instruction *RNDD(dst_reg dst, src_reg src0);
350 vec4_instruction *RNDE(dst_reg dst, src_reg src0);
351 vec4_instruction *RNDZ(dst_reg dst, src_reg src0);
352 vec4_instruction *FRC(dst_reg dst, src_reg src0);
[all …]
Dbrw_eu_emit.c743 struct brw_reg src0, in brw_alu2() argument
748 brw_set_src0(p, insn, src0); in brw_alu2()
767 struct brw_reg src0, in brw_alu3() argument
788 assert(src0.file == BRW_GENERAL_REGISTER_FILE); in brw_alu3()
789 assert(src0.address_mode == BRW_ADDRESS_DIRECT); in brw_alu3()
790 assert(src0.nr < 128); in brw_alu3()
791 assert(src0.type == BRW_REGISTER_TYPE_F); in brw_alu3()
792 insn->bits2.da3src.src0_swizzle = src0.dw1.bits.swizzle; in brw_alu3()
793 insn->bits2.da3src.src0_subreg_nr = get_3src_subreg_nr(src0); in brw_alu3()
794 insn->bits2.da3src.src0_reg_nr = src0.nr; in brw_alu3()
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Dbrw_fs.h146 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0);
147 fs_inst(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
149 fs_reg src0, fs_reg src1,fs_reg src2);
221 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0);
222 fs_inst *emit(enum opcode opcode, fs_reg dst, fs_reg src0, fs_reg src1);
224 fs_reg src0, fs_reg src1, fs_reg src2);
277 struct brw_reg src0,
284 struct brw_reg src0,
316 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
317 fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
Dbrw_wm_fp.c207 struct prog_src_register src0, in emit_tex_op() argument
226 inst->SrcReg[0] = src0; in emit_tex_op()
237 struct prog_src_register src0, in emit_op() argument
243 src0, src1, src2); in emit_op()
559 struct prog_src_register src0 = inst->SrcReg[0]; in precalc_dst() local
571 src0, in precalc_dst()
578 GLuint z = GET_SWZ(src0.Swizzle, Z); in precalc_dst()
586 src_swizzle(src0, SWIZZLE_ONE, z, z, z), in precalc_dst()
623 struct prog_src_register src0 = inst->SrcReg[0]; in precalc_lit() local
631 src0, in precalc_lit()
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Dbrw_fs_emit.cpp170 struct brw_reg src0) in generate_math1_gen7() argument
175 0, src0, in generate_math1_gen7()
183 struct brw_reg src0, in generate_math2_gen7() argument
187 brw_math2(p, dst, brw_math_function(inst->opcode), src0, src1); in generate_math2_gen7()
193 struct brw_reg src0) in generate_math1_gen6() argument
202 0, src0, in generate_math1_gen6()
210 0, sechalf(src0), in generate_math1_gen6()
220 struct brw_reg src0, in generate_math2_gen6() argument
228 brw_math2(p, dst, op, src0, src1); in generate_math2_gen6()
232 brw_math2(p, sechalf(dst), op, sechalf(src0), sechalf(src1)); in generate_math2_gen6()
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/external/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_insn.c296 struct src_register *src0) in emit_repl() argument
303 src0_swizzle = src0->base.swizzle; in emit_repl()
312 src0->base.swizzle = SVGA3DSWIZZLE_NONE; in emit_repl()
314 if (!emit_op1( emit, inst_token( SVGA3DOP_MOV ), dst, *src0 )) in emit_repl()
317 *src0 = src( dst ); in emit_repl()
318 src0->base.swizzle = src0_swizzle; in emit_repl()
335 struct src_register src0 ) in submit_op1() argument
337 return emit_op1( emit, inst, dest, src0 ); in submit_op1()
351 struct src_register src0, in submit_op2() argument
359 type0 = SVGA3dShaderGetRegType( src0.base.value ); in submit_op2()
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Dsvga_tgsi_emit.h183 struct src_register src0 ) in emit_op1() argument
187 emit_src( emit, src0 )); in emit_op1()
193 struct src_register src0, in emit_op2() argument
198 emit_src( emit, src0 ) && in emit_op2()
205 struct src_register src0, in emit_op3() argument
211 emit_src( emit, src0 ) && in emit_op3()
220 struct src_register src0, in emit_op4() argument
227 emit_src( emit, src0 ) && in emit_op4()
/external/mesa3d/src/gallium/drivers/i915/
Di915_fpc_translate.c498 uint src0, src1, src2, flags; in i915_translate_instruction() local
503 src0 = src_vector(p, &inst->Src[0], fs); in i915_translate_instruction()
508 src0, negate(src0, 1, 1, 1, 1), 0); in i915_translate_instruction()
516 src0 = src_vector(p, &inst->Src[0], fs); in i915_translate_instruction()
523 negate(src0, 1, 1, 1, 1), 0, 0); in i915_translate_instruction()
532 src0 = src_vector(p, &inst->Src[0], fs); in i915_translate_instruction()
538 0, src0, src2, src1); /* NOTE: order of src2, src1 */ in i915_translate_instruction()
542 src0 = src_vector(p, &inst->Src[0], fs); in i915_translate_instruction()
548 src0, i915_emit_const1f(p, 1.0f / (float) (M_PI * 2.0)), 0); in i915_translate_instruction()
588 src0 = get_result_vector(p, &inst->Dst[0]); in i915_translate_instruction()
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/external/mesa3d/src/mesa/drivers/dri/i915/
Di915_fragprog.c409 GLuint src0, src1, src2, flags; in upload_program() local
414 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
419 src0, negate(src0, 1, 1, 1, 1), 0); in upload_program()
427 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
430 …i915_emit_arith(p, A0_CMP, get_result_vector(p, inst), get_result_flags(inst), 0, src0, src2, src1… in upload_program()
434 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
443 src0, in upload_program()
513 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
519 swizzle(src0, X, Y, ZERO, ZERO), in upload_program()
533 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program()
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/external/llvm/lib/Target/R600/
DEvergreenInstructions.td263 // [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))]
281 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))],
286 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))],
293 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))],
307 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))],
312 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU
331 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU
367 let src0 = 0;
427 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel,
430 " "#name#" $last OQAP, $src0$src0_rel $pred_sel",
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DAMDGPUInstructions.td447 (ins rc:$src0),
448 "CLAMP $dst, $src0",
449 [(set f32:$dst, (AMDGPUclamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
454 (ins rc:$src0),
455 "FABS $dst, $src0",
456 [(set f32:$dst, (fabs f32:$src0))]
461 (ins rc:$src0),
462 "FNEG $dst, $src0",
463 [(set f32:$dst, (fneg f32:$src0))]
499 (fpow f32:$src0, f32:$src1),
[all …]
DR600Instructions.td97 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
102 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
128 [(set R600_Reg32:$dst, (node R600_Reg32:$src0))], itin
139 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, ABS:$src0_abs, SEL:$src0_sel,
145 "$src0_neg$src0_abs$src0$src0_abs$src0_rel, "
166 [(set R600_Reg32:$dst, (node R600_Reg32:$src0,
178 R600_Reg32:$src0, NEG:$src0_neg, REL:$src0_rel, SEL:$src0_sel,
184 "$src0_neg$src0$src0_rel, "
350 (ins i32imm:$src0, R600_TReg32_Y:$src1, R600_TReg32_X:$src2),
351 "INTERP_PAIR_XY $src0 $src1 $src2 : $dst0 dst1",
[all …]
DSIInstrInfo.td462 VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
463 "exp $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
520 op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
521 opName#" $dst, $src0", pattern
525 op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
526 opName#" $dst, $src0", pattern
546 def "" : SOP1_Pseudo <opName, (outs), (ins SReg_64:$src0), pattern>;
548 def _si : SOP1_Real_si <op, opName, (outs), (ins SReg_64:$src0),
549 opName#" $src0"> {
553 def _vi : SOP1_Real_vi <op, opName, (outs), (ins SReg_64:$src0),
[all …]
/external/opencv/cv/src/
Dcvderiv.cpp575 const int *src0 = src[-1], *src1 = src[0], *src2 = src[1]; in icvLaplaceCol_32s16s() local
580 int s0 = src0[i] - src1[i]*2 + src2[i] + src1[i+width]; in icvLaplaceCol_32s16s()
581 int s1 = src0[i+1] - src1[i+1]*2 + src2[i+1] + src1[i+width+1]; in icvLaplaceCol_32s16s()
586 dst[i] = (short)(src0[i] - src1[i]*2 + src2[i] + src1[i+width]); in icvLaplaceCol_32s16s()
591 int s0 = src0[i] - src1[i]*2 + src2[i] + in icvLaplaceCol_32s16s()
592 src0[i+width] + src1[i+width]*2 + src2[i+width]; in icvLaplaceCol_32s16s()
593 int s1 = src0[i+1] - src1[i+1]*2 + src2[i+1] + in icvLaplaceCol_32s16s()
594 src0[i+width+1] + src1[i+width+1]*2 + src2[i+width+1]; in icvLaplaceCol_32s16s()
600 int s0 = CV_DESCALE(src0[i] - src1[i]*2 + src2[i] + in icvLaplaceCol_32s16s()
601 src0[i+width] + src1[i+width]*2 + src2[i+width], 2); in icvLaplaceCol_32s16s()
[all …]
/external/llvm/test/CodeGen/R600/
Dllvm.AMDGPU.umad24.ll15 define void @test_umad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
16 %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone
29 %src0.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
30 %src2.gep = getelementptr i32, i32 addrspace(1)* %src0.gep, i32 1
32 %src0 = load i32, i32 addrspace(1)* %src0.gep, align 4
34 %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 4, i32 %src2) nounwind readnone
Dllvm.AMDGPU.bfi.ll10 define void @bfi_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
11 %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 %src1, i32 %src1) nounwind readnone
19 define void @bfi_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind {
20 %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 %src1, i32 123) nounwind readnone
28 define void @bfi_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind {
29 %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 123, i32 %src2) nounwind readnone
/external/pdfium/core/src/fxcodec/jbig2/
DJBig2_Image.cpp202 FX_DWORD src0, src1, src, dest, s1, s2, m1, m2, m3; in composeTo_opt() local
382 src0 = src1; in composeTo_opt()
384 src = (((src0 << 8) | src1) >> s1) & 0xff; in composeTo_opt()
389 src0 = src1; in composeTo_opt()
395 src = (((src0 << 8) | src1) >> s1) & 0xff; in composeTo_opt()
414 src0 = src1; in composeTo_opt()
416 src = (((src0 << 8) | src1) >> s1) & 0xff; in composeTo_opt()
421 src0 = src1; in composeTo_opt()
427 src = (((src0 << 8) | src1) >> s1) & 0xff; in composeTo_opt()
446 src0 = src1; in composeTo_opt()
[all …]
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_vertprog.c369 #define ZERO_SRC_0 (((o_inst->src0 & ~(0xfff << R200_VPI_IN_X_SHIFT)) \
387 #define UNUSED_SRC_0 ((o_inst->src0 & ~15) | 9)
655 o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[2]), in r200_translate_vertex_program()
677 o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), in r200_translate_vertex_program()
713 o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), in r200_translate_vertex_program()
727 o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), in r200_translate_vertex_program()
742 o_inst->src0 = MAKE_VSF_SOURCE(u_temp_i, in r200_translate_vertex_program()
759 o_inst->src0 = t_src(vp, &src[0]); in r200_translate_vertex_program()
778 o_inst->src0 = t_src(vp, &src[0]); in r200_translate_vertex_program()
805 o_inst->src0 = MAKE_VSF_SOURCE(t_src_index(vp, &src[0]), in r200_translate_vertex_program()
[all …]

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