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Searched refs:EmitR (Results 1 – 4 of 4) sorted by relevance

/art/compiler/utils/mips64/
Dassembler_mips64.cc33 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR() function in art::mips64::Mips64Assembler
95 EmitR(0, rs, rt, rd, 0, 0x20); in Add()
103 EmitR(0, rs, rt, rd, 0, 0x21); in Addu()
111 EmitR(0, rs, rt, rd, 0, 0x2d); in Daddu()
119 EmitR(0, rs, rt, rd, 0, 0x22); in Sub()
123 EmitR(0, rs, rt, rd, 0, 0x23); in Subu()
127 EmitR(0, rs, rt, rd, 0, 0x2f); in Dsubu()
131 EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x18); in MultR2()
135 EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x19); in MultuR2()
139 EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1a); in DivR2()
[all …]
Dassembler_mips64.h344 void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct);
/art/compiler/utils/mips/
Dassembler_mips.cc42 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { in EmitR() function in art::mips::MipsAssembler
164 EmitR(0, rs, rt, rd, 0, 0x20); in Add()
168 EmitR(0, rs, rt, rd, 0, 0x21); in Addu()
180 EmitR(0, rs, rt, rd, 0, 0x22); in Sub()
184 EmitR(0, rs, rt, rd, 0, 0x23); in Subu()
188 EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x18); in Mult()
192 EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x19); in Multu()
196 EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x1a); in Div()
200 EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x1b); in Divu()
204 EmitR(0, rs, rt, rd, 0, 0x24); in And()
[all …]
Dassembler_mips.h271 void EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);