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Searched refs:op (Results 1 – 25 of 38) sorted by relevance

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/art/compiler/optimizing/
Dgraph_checker.cc536 void SSAChecker::VisitCondition(HCondition* op) { in VisitCondition() argument
537 VisitInstruction(op); in VisitCondition()
538 if (op->GetType() != Primitive::kPrimBoolean) { in VisitCondition()
541 op->DebugName(), op->GetId(), in VisitCondition()
542 Primitive::PrettyDescriptor(op->GetType()))); in VisitCondition()
544 HInstruction* lhs = op->InputAt(0); in VisitCondition()
545 HInstruction* rhs = op->InputAt(1); in VisitCondition()
549 op->DebugName(), op->GetId(), in VisitCondition()
553 if (!op->IsEqual() && !op->IsNotEqual()) { in VisitCondition()
557 op->DebugName(), op->GetId())); in VisitCondition()
[all …]
Dgraph_checker.h118 void VisitBinaryOperation(HBinaryOperation* op) OVERRIDE;
119 void VisitCondition(HCondition* op) OVERRIDE;
/art/compiler/dex/quick/mips/
Dfp_mips.cc28 int op = kMipsNop; in GenArithOpFloat() local
38 op = kMipsFadds; in GenArithOpFloat()
42 op = kMipsFsubs; in GenArithOpFloat()
46 op = kMipsFdivs; in GenArithOpFloat()
50 op = kMipsFmuls; in GenArithOpFloat()
68 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpFloat()
74 int op = kMipsNop; in GenArithOpDouble() local
80 op = kMipsFaddd; in GenArithOpDouble()
84 op = kMipsFsubd; in GenArithOpDouble()
88 op = kMipsFdivd; in GenArithOpDouble()
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Dutility_mips.cc280 LIR* MipsMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg() argument
282 switch (op) { in OpReg()
295 LIR* MipsMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm() argument
296 if ((op == kOpAdd) || (op == kOpSub)) { in OpRegImm()
297 return OpRegRegImm(op, r_dest_src1, r_dest_src1, value); in OpRegImm()
304 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg() argument
307 switch (op) { in OpRegRegReg()
346 LIR* MipsMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) { in OpRegRegImm() argument
352 switch (op) { in OpRegRegImm()
466 LIR* MipsMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg() argument
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Dcodegen_mips.h203 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
205 LIR* OpReg(OpKind op, RegStorage r_dest_src);
208 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
209 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
212 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
213 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
214 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
239 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
276 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
/art/test/004-ThreadStress/src/
DMain.java256 Operation op = null; in updateFrequencyMap() local
258 op = new OOM(); in updateFrequencyMap()
260 op = new SigQuit(); in updateFrequencyMap()
262 op = new Alloc(); in updateFrequencyMap()
264 op = new StackTrace(); in updateFrequencyMap()
266 op = new Exit(); in updateFrequencyMap()
268 op = new Sleep(); in updateFrequencyMap()
270 op = new Wait(lock); in updateFrequencyMap()
272 op = new TimedWait(lock); in updateFrequencyMap()
280 in.put(op, d); in updateFrequencyMap()
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/art/compiler/dex/quick/arm64/
Dfp_arm64.cc28 int op = kA64Brk1d; in GenArithOpFloat() local
34 op = kA64Fadd3fff; in GenArithOpFloat()
38 op = kA64Fsub3fff; in GenArithOpFloat()
42 op = kA64Fdiv3fff; in GenArithOpFloat()
46 op = kA64Fmul3fff; in GenArithOpFloat()
64 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpFloat()
70 int op = kA64Brk1d; in GenArithOpDouble() local
76 op = kA64Fadd3fff; in GenArithOpDouble()
80 op = kA64Fsub3fff; in GenArithOpDouble()
84 op = kA64Fdiv3fff; in GenArithOpDouble()
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Dutility_arm64.cc491 A64Opcode op; in LoadConstantWide() local
497 op = WIDE(kA64Movn3rdM); in LoadConstantWide()
500 op = WIDE(kA64Movz3rdM); in LoadConstantWide()
509 res = NewLIR3(op, r_dest.GetReg(), halfword ^ background, shift); in LoadConstantWide()
552 LIR* Arm64Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg() argument
554 switch (op) { in OpReg()
559 LOG(FATAL) << "Bad opcode " << op; in OpReg()
564 LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) { in OpRegRegShift() argument
569 switch (op) { in OpRegRegShift()
612 return OpRegRegRegShift(op, r_dest_src1, r_dest_src1, r_src2, shift); in OpRegRegShift()
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Dcodegen_arm64.h209 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
211 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
214 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
215 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
218 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
219 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE;
220 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
265 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
367 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
369 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value);
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Darm64_lir.h379 #define WIDE(op) ((A64Opcode)((op) | kA64Wide)) argument
380 #define UNWIDE(op) ((A64Opcode)((op) & ~kA64Wide)) argument
383 #define IS_WIDE(op) (((op) & kA64Wide) != 0) argument
/art/compiler/dex/quick/x86/
Dutility_x86.cc126 LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg() argument
128 switch (op) { in OpReg()
134 LOG(FATAL) << "Bad case in OpReg " << op; in OpReg()
139 LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm() argument
144 switch (op) { in OpRegImm()
152 LOG(FATAL) << "Bad case in OpRegImm (64-bit) " << op; in OpRegImm()
155 switch (op) { in OpRegImm()
195 LOG(FATAL) << "Bad case in OpRegImm " << op; in OpRegImm()
201 LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg() argument
205 switch (op) { in OpRegReg()
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Dint_x86.cc1949 Instruction::Code op) { in GenLongRegOrMemOp() argument
1951 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); in GenLongRegOrMemOp()
1967 x86op = GetOpcode(op, rl_dest, rl_src, true); in GenLongRegOrMemOp()
1985 x86op = GetOpcode(op, rl_dest, rl_src, true); in GenLongRegOrMemOp()
1992 void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { in GenLongArith() argument
1999 GenLongRegOrMemOp(rl_result, rl_src, op); in GenLongArith()
2007 GenLongRegOrMemOp(rl_result, rl_src, op); in GenLongArith()
2018 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); in GenLongArith()
2030 x86op = GetOpcode(op, rl_dest, rl_src, true); in GenLongArith()
2050 RegLocation rl_src2, Instruction::Code op, in GenLongArith() argument
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Dcodegen_x86.h218 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
229 Instruction::Code op);
239 Instruction::Code op, bool is_commutative);
247 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
255 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
302 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
304 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
307 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
308 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
311 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
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Dfp_x86.cc28 X86OpCode op = kX86Nop; in GenArithOpFloat() local
38 op = kX86AddssRR; in GenArithOpFloat()
42 op = kX86SubssRR; in GenArithOpFloat()
46 op = kX86DivssRR; in GenArithOpFloat()
50 op = kX86MulssRR; in GenArithOpFloat()
73 NewLIR2(op, r_dest.GetReg(), r_src2.GetReg()); in GenArithOpFloat()
85 X86OpCode op = kX86Nop; in GenArithOpDouble() local
91 op = kX86AddsdRR; in GenArithOpDouble()
95 op = kX86SubsdRR; in GenArithOpDouble()
99 op = kX86DivsdRR; in GenArithOpDouble()
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/art/compiler/dex/quick/arm/
Dfp_arm.cc28 int op = kThumbBkpt; in GenArithOpFloat() local
38 op = kThumb2Vadds; in GenArithOpFloat()
42 op = kThumb2Vsubs; in GenArithOpFloat()
46 op = kThumb2Vdivs; in GenArithOpFloat()
50 op = kThumb2Vmuls; in GenArithOpFloat()
68 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpFloat()
74 int op = kThumbBkpt; in GenArithOpDouble() local
80 op = kThumb2Vaddd; in GenArithOpDouble()
84 op = kThumb2Vsubd; in GenArithOpDouble()
88 op = kThumb2Vdivd; in GenArithOpDouble()
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Dutility_arm.cc270 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg() argument
272 switch (op) { in OpReg()
280 LOG(FATAL) << "Bad opcode " << op; in OpReg()
285 LIR* ArmMir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, in OpRegRegShift() argument
290 switch (op) { in OpRegRegShift()
398 LOG(FATAL) << "Bad opcode: " << op; in OpRegRegShift()
418 LIR* ArmMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg() argument
419 return OpRegRegShift(op, r_dest_src1, r_src2, 0); in OpRegReg()
434 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg() argument
435 UNUSED(op, cc, r_dest, r_src); in OpCondRegReg()
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Dcodegen_arm.h206 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
208 LIR* OpReg(OpKind op, RegStorage r_dest_src);
211 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
212 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
215 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
216 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
217 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
225 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
227 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
272 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
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Dint_arm.cc580 bool ArmMir2Lir::GetEasyMultiplyOp(int lit, ArmMir2Lir::EasyMultiplyOp* op) { in GetEasyMultiplyOp() argument
585 op->op = kOpInvalid; in GetEasyMultiplyOp()
586 op->shift = 0; in GetEasyMultiplyOp()
591 op->op = kOpLsl; in GetEasyMultiplyOp()
592 op->shift = CTZ(lit); in GetEasyMultiplyOp()
597 op->op = kOpAdd; in GetEasyMultiplyOp()
598 op->shift = CTZ(lit - 1); in GetEasyMultiplyOp()
603 op->op = kOpRsub; in GetEasyMultiplyOp()
604 op->shift = CTZ(lit + 1); in GetEasyMultiplyOp()
608 op->op = kOpInvalid; in GetEasyMultiplyOp()
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/art/disassembler/
Ddisassembler_arm64.cc68 vixl::Instr op = instr->Mask(vixl::LoadLiteralMask); in VisitLoadLiteral() local
70 switch (op) { in VisitLoadLiteral()
74 int64_t data = op == vixl::LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address) in VisitLoadLiteral()
81 double data = (op == vixl::LDR_s_lit) ? *reinterpret_cast<float*>(data_address) in VisitLoadLiteral()
Ddisassembler_arm.cc273 uint32_t op = (instruction >> 21) & 0xf; in DumpArm() local
274 opcode = kDataProcessingOperations[op]; in DumpArm()
275 bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN. in DumpArm()
276 bool is_mov = op == 13U /* 0b1101 */ || op == 15U /* 0b1111 */; in DumpArm()
505 uint32_t op = (instr >> 23) & 3; in DumpThumb32() local
509 if (op == 1 || op == 2) { in DumpThumb32()
510 if (op == 1) { in DumpThumb32()
924 uint32_t op = (instr >> 7) & 1; in DumpThumb32() local
931 opcode << (op == 0 ? "vmov" : "vabs") << (S != 0 ? ".f64" : ".f32"); in DumpThumb32()
934 opcode << (op != 0 ? "vsqrt" : "vneg") << (S != 0 ? ".f64" : ".f32"); in DumpThumb32()
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Ddisassembler_mips.cc332 uint32_t op = (instruction >> 26) & 0x3f; in Dump() local
334 opcode = StringPrintf("op=%d fn=%d", op, function); in Dump()
429 if (((op == 0x36 && rs == 0 && rt != 0) || // jic in Dump()
430 (op == 0x19 && rs == rt && rt != 0)) && // daddiu in Dump()
437 if (op == 0x36) { in Dump()
/art/compiler/dex/
Dglobal_value_numbering.h94 static uint64_t BuildKey(uint16_t op, uint16_t operand1, uint16_t operand2, uint16_t modifier) { in BuildKey() argument
95 return (static_cast<uint64_t>(op) << 48 | static_cast<uint64_t>(operand1) << 32 | in BuildKey()
100 uint16_t LookupValue(uint16_t op, uint16_t operand1, uint16_t operand2, uint16_t modifier) { in LookupValue() argument
102 uint64_t key = BuildKey(op, operand1, operand2, modifier); in LookupValue()
114 uint16_t FindValue(uint16_t op, uint16_t operand1, uint16_t operand2, uint16_t modifier) const { in FindValue() argument
116 uint64_t key = BuildKey(op, operand1, operand2, modifier); in FindValue()
/art/test/701-easy-div-rem/
DgenMain.py57 for op, op_name in (('/', 'Div'), ('%', 'Rem')):
58 local_vars['@OP@'] = op
/art/compiler/dex/quick/
Dgen_common.cc464 OpKind op = kOpInvalid; in GenIntNarrowing() local
467 op = kOp2Byte; in GenIntNarrowing()
470 op = kOp2Short; in GenIntNarrowing()
473 op = kOp2Char; in GenIntNarrowing()
478 OpRegReg(op, rl_result.reg, rl_src.reg); in GenIntNarrowing()
1519 OpKind op = kOpBkpt; in GenArithOpInt() local
1527 op = kOpNeg; in GenArithOpInt()
1531 op = kOpMvn; in GenArithOpInt()
1536 op = kOpAdd; in GenArithOpInt()
1540 op = kOpSub; in GenArithOpInt()
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/art/test/000-nop/
Dinfo.txt1 This is a sample no-op test, which does at least serve to verify that the

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