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Searched refs:D15 (Results 1 – 25 of 44) sorted by relevance

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/external/libhevc/decoder/arm/
Dihevcd_fmt_conv_420sp_to_rgba8888.s227 VQMOVUN.S16 D15,Q9
231 VZIP.8 D14,D15
249 VST1.32 D15,[R2]!
278 VQMOVUN.S16 D15,Q9
282 VZIP.8 D14,D15
300 VST1.32 D15,[R8]!
358 VQMOVUN.S16 D15,Q9
362 VZIP.8 D14,D15
380 VST1.32 D15,[R2]!
400 VQMOVUN.S16 D15,Q9
[all …]
/external/libhevc/common/arm/
Dihevc_sao_edge_offset_class0_chroma.s153 …VMOV.16 D15[3],r11 @vsetq_lane_u16(pu1_src_left[ht - row], pu1_cur_row_tmp, 1…
207 VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
211 VUZP.8 D14,D15
218 VTBL.8 D17,{D0},D15
241 VMOVN.I16 D15,Q6 @vmovn_s16(pi2_tmp_cur_row.val[1])
261 VST1.8 {D14,D15},[r12],r1 @vst1q_u8(pu1_src_cpy, pu1_cur_row)
316 …VMOV.16 D15[3],r11 @vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15)
372 VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
376 VUZP.8 D14,D15
383 VTBL.8 D17,{D0},D15
Dihevc_sao_band_offset_chroma.s176 VCLE.U8 D15,D2,D30 @vcle_u8(band_table.val[1], vdup_n_u8(16))
178 VORR.U8 D2,D2,D15 @band_table.val[1] = vorr_u8(band_table.val[1], au1_cmp)
189 VAND.U8 D2,D2,D15 @band_table.val[1] = vand_u8(band_table.val[1], au1_cmp)
210 …VADD.I8 D15,D11,D30 @band_table_v.val[2] = vadd_u8(band_table_v.val[2], band_p…
222 …VADD.I8 D11,D15,D27 @band_table_v.val[2] = vadd_u8(band_table_v.val[2], vdup_n…
296 VSUB.I8 D15,D13,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
304 …VTBX.8 D13,{D1-D4},D15 @vtbx4_u8(au1_cur_row_deint.val[0], band_table_u, vsub_u8(…
350 VSUB.I8 D15,D13,D31 @vsub_u8(au1_cur_row_deint.val[0], band_pos_u)
358 …VTBX.8 D13,{D1-D4},D15 @vtbx4_u8(au1_cur_row_deint.val[0], band_table_u, vsub_u8(…
Dihevc_sao_band_offset_luma.s195 VLD1.8 D15,[r5] @au1_cur_row = vld1_u8(pu1_src_cpy)
203 VSUB.I8 D16,D15,D31 @vsub_u8(au1_cur_row, band_pos)
205 …VTBX.8 D15,{D1-D4},D16 @vtbx4_u8(au1_cur_row, band_table, vsub_u8(au1_cur_row, ba…
214 VST1.8 D15,[r5] @vst1_u8(pu1_src_cpy, au1_cur_row)
Dihevc_sao_edge_offset_class0.s147 …VMOV.8 D15[7],r11 @vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15)
206 VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
224 VTBL.8 D17,{D11},D15 @offset = vtbl1_s8(offset_tbl, vget_high_s8(edge_idx))
294 …VMOV.8 D15[7],r11 @vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15)
Dihevc_sao_edge_offset_class3_chroma.s387 …VMOV.8 D15[6],r8 @I sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[14] …
390 …VMOV.8 D15[7],r9 @I sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] -pu1_src_c…
468 …VMOV.8 D15[6],r10 @II sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[14]…
473 …VMOV.8 D15[7],r8 @II sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] -pu1_src_…
519 …VMOV.8 D15[6],r9 @III sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[14…
522 …VMOV.8 D15[7],r10 @III sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] -pu1_src…
623 …VMOV.8 D15[6],r8 @sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[14] -p…
627 …VMOV.8 D15[7],r10 @sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] -pu1_src_cpy…
792 …VMOV.8 D15[6],r8 @sign_up = sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[14] -p…
796 …VMOV.8 D15[7],r10 @sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] -pu1_src_cpy…
[all …]
Dihevc_sao_edge_offset_class3.s305 …VMOV.8 D15[7],r8 @I sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] - pu1_src_…
374 …VMOV.8 D15[7],r11 @II sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] - pu1_src…
412 …VMOV.8 D15[7],r2 @III sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] - pu1_sr…
504 …VMOV.8 D15[7],r8 @sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] - pu1_src_cp…
645 …VMOV.8 D15[7],r8 @sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] - pu1_src_cp…
783 …VMOV.8 D15[7],r8 @sign_up = vsetq_lane_s8(SIGN(pu1_src_cpy[15] - pu1_src_cp…
/external/llvm/test/MC/MachO/
Dx86_32-symbols.s50 D15: label
/external/llvm/lib/Target/ARM/
DARMBaseRegisterInfo.h63 case D15: case D14: case D13: case D12: in isARMArea3Register()
DARMRegisterInfo.td115 def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>;
145 def Q7 : ARMReg< 7, "q7", [D14, D15]>;
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td106 def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>;
174 (sequence "D%u", 6, 13), D5, D14, D15)>;
DHexagonRegisterInfo.cpp69 Reserved.set(Hexagon::D15); in getReservedRegs()
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td144 def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>;
173 def Q7 : Rq<28, "F28", [D14, D15]>;
/external/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp157 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15 in DecodeDoubleRegsRegisterClass()
/external/llvm/lib/Target/AArch64/Utils/
DAArch64BaseInfo.h126 case AArch64::D15: return AArch64::B15; in getBRegFromDReg()
166 case AArch64::B15: return AArch64::D15; in getDRegFromBReg()
/external/llvm/lib/Target/AArch64/
DAArch64CallingConvention.td236 CCIfType<[f64], CCAssignToReg<[D12, D13, D14, D15]>>,
256 D12, D13, D14, D15)>;
DAArch64PBQPRegAlloc.cpp71 case AArch64::D15: in isOdd()
DAArch64RegisterInfo.td331 def D15 : AArch64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
366 def Q15 : AArch64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias<B15>;
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AsmBackend.cpp426 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15) in generateCompactUnwindEncoding()
/external/llvm/lib/Target/Sparc/Disassembler/
DSparcDisassembler.cpp94 SP::D14, SP::D30, SP::D15, SP::D31 };
/external/valgrind/
DREADME.aarch64155 I think what is required is to save D8-D15 and nothing more than that.
/external/valgrind/memcheck/
Dmc_machine.c889 if (o >= GOF(D15) && o+sz <= GOF(D15)+SZB(D15)) return GOF(D15); in get_otrack_shadow_offset_wrk()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp115 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
/external/libavc/encoder/arm/
Dime_distortion_metrics_a9q.s900 @;Q7 -> D14:D15
921 @;D15 : sad_left
/external/llvm/lib/Target/Mips/
DMipsRegisterInfo.td368 D10, D11, D12, D13, D14, D15)>;

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