| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64ExternalSymbolizer.cpp | 107 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
116 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
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| /external/llvm/test/CodeGen/ARM/ |
| D | jump-table-islands-split.ll | 8 ; eliminate the entry calculation (ADD) and use the ADR as the base.
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| /external/vixl/src/vixl/a64/ |
| D | instructions-a64.cc | 305 VIXL_ASSERT(Mask(PCRelAddressingMask) == ADR); in ImmPCOffsetTarget()
340 if ((Mask(PCRelAddressingMask) == ADR)) { in SetPCRelImmTarget()
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| D | constants-a64.h | 448 ADR = PCRelAddressingFixed | 0x00000000, enumerator
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| D | disasm-a64.cc | 534 case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break; in VisitPCRelAddressing()
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| D | simulator-a64.cc | 814 VIXL_ASSERT((instr->Mask(PCRelAddressingMask) == ADR) || in VisitPCRelAddressing()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopRerollPass.cpp | 842 const auto *ADR = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(V.BaseInst)); in findRoots() local
843 if (!ADR) in findRoots()
857 const SCEV *StepSCEV = SE->getMinusSCEV(SE->getSCEV(V.Roots[0]), ADR); in findRoots()
859 if (ADR->getStepRecurrence(*SE) != SE->getMulExpr(StepSCEV, ScaleSCEV)) { in findRoots()
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| /external/v8/src/arm64/ |
| D | instructions-arm64.h | 197 return Mask(PCRelAddressingMask) == ADR; in IsAdr()
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| D | constants-arm64.h | 421 ADR = PCRelAddressingFixed | 0x00000000, enumerator
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| D | disasm-arm64.cc | 521 case ADR: Format(instr, "adr", "'Xd, 'AddrPCRelByte"); break; in VisitPCRelAddressing()
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| D | assembler-arm64.cc | 1082 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
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| D | simulator-arm64.cc | 1302 case ADR: in VisitPCRelAddressing()
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb1.txt | 55 # ADR
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| D | thumb2.txt | 91 # ADR
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| D | basic-arm-instructions.txt | 187 # ADR
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| /external/tremolo/Tremolo/ |
| D | dpen.s | 63 ADR r14,dpen_read_return
458 ADR r6,.Lcrc_lookup
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| D | mdctARM.s | 1003 ADR r6, bitrev
1033 ADR r7, .Lsincos_lookup @ sincos_lookup0 +
1127 ADR r7, .Lsincos_lookup @ sincos_lookup0 +
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| D | mdctLARM.s | 989 ADR r6, bitrev
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64MCCodeEmitter.cpp | 247 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR in getAdrLabelOpValue()
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb-instructions.s | 86 @ ADR
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| /external/llvm/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 1262 : ARM::ADR)) in EmitInstruction()
1278 : ARM::ADR)) in EmitInstruction()
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| D | ARMScheduleSwift.td | 127 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
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| D | ARMInstrThumb.td | 117 // ADR instruction labels.
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 136 // ADR,ADRP
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| /external/vixl/doc/ |
| D | supported-instructions.md | 48 ### ADR ### subsection
55 ### ADR ### subsection
|