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Searched refs:BEGIN_BATCH (Results 1 – 25 of 50) sorted by relevance

12

/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen7_disable.c37 BEGIN_BATCH(7); in disable_stages()
47 BEGIN_BATCH(7); in disable_stages()
62 BEGIN_BATCH(2); in disable_stages()
68 BEGIN_BATCH(7); in disable_stages()
78 BEGIN_BATCH(7); in disable_stages()
88 BEGIN_BATCH(2); in disable_stages()
94 BEGIN_BATCH(4); in disable_stages()
102 BEGIN_BATCH(7); in disable_stages()
112 BEGIN_BATCH(6); in disable_stages()
121 BEGIN_BATCH(2); in disable_stages()
Dbrw_misc_state.c51 BEGIN_BATCH(4); in upload_drawing_rect()
80 BEGIN_BATCH(6); in upload_binding_table_pointers()
114 BEGIN_BATCH(4); in upload_gen6_binding_table_pointers()
151 BEGIN_BATCH(1); in upload_pipelined_state_pointers()
156 BEGIN_BATCH(7); in upload_pipelined_state_pointers()
355 BEGIN_BATCH(len); in emit_depthbuffer()
421 BEGIN_BATCH(len); in emit_depthbuffer()
481 BEGIN_BATCH(len); in emit_depthbuffer()
526 BEGIN_BATCH(3); in emit_depthbuffer()
534 BEGIN_BATCH(3); in emit_depthbuffer()
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Dgen7_blorp.cpp72 BEGIN_BATCH(2); in gen7_blorp_emit_blend_state_pointer()
87 BEGIN_BATCH(2); in gen7_blorp_emit_cc_state_pointer()
107 BEGIN_BATCH(2); in gen7_blorp_emit_cc_viewport()
125 BEGIN_BATCH(2); in gen7_blorp_emit_depth_stencil_state_pointers()
288 BEGIN_BATCH(7); in gen7_blorp_emit_hs_disable()
310 BEGIN_BATCH(4); in gen7_blorp_emit_te_disable()
329 BEGIN_BATCH(6); in gen7_blorp_emit_ds_disable()
350 BEGIN_BATCH(3); in gen7_blorp_emit_streamout_disable()
383 BEGIN_BATCH(7); in gen7_blorp_emit_sf_config()
397 BEGIN_BATCH(14); in gen7_blorp_emit_sf_config()
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Dgen6_blorp.cpp98 BEGIN_BATCH(1); in gen6_blorp_emit_batch_head()
123 BEGIN_BATCH(10); in gen6_blorp_emit_state_base_address()
213 BEGIN_BATCH(batch_length); in gen6_blorp_emit_vertices()
235 BEGIN_BATCH(batch_length); in gen6_blorp_emit_vertices()
280 BEGIN_BATCH(3); in gen6_blorp_emit_urb_config()
380 BEGIN_BATCH(4); in gen6_blorp_emit_cc_state_pointers()
568 BEGIN_BATCH(4); in gen6_blorp_emit_sampler_state_pointers()
603 BEGIN_BATCH(6); in gen6_blorp_emit_vs_disable()
624 BEGIN_BATCH(7); in gen6_blorp_emit_gs_disable()
656 BEGIN_BATCH(4); in gen6_blorp_emit_clip_disable()
[all …]
Dgen7_urb.c57 BEGIN_BATCH(2); in gen7_allocate_push_constants()
62 BEGIN_BATCH(2); in gen7_allocate_push_constants()
113 BEGIN_BATCH(2); in gen7_emit_urb_state()
121 BEGIN_BATCH(2); in gen7_emit_urb_state()
127 BEGIN_BATCH(2); in gen7_emit_urb_state()
133 BEGIN_BATCH(2); in gen7_emit_urb_state()
Dgen7_vs_state.c43 BEGIN_BATCH(2); in upload_vs_state()
49 BEGIN_BATCH(2); in upload_vs_state()
56 BEGIN_BATCH(7); in upload_vs_state()
66 BEGIN_BATCH(7); in upload_vs_state()
86 BEGIN_BATCH(6); in upload_vs_state()
Dgen7_misc_state.c146 BEGIN_BATCH(7); in emit_depthbuffer()
190 BEGIN_BATCH(7); in emit_depthbuffer()
210 BEGIN_BATCH(3); in emit_depthbuffer()
221 BEGIN_BATCH(3); in emit_depthbuffer()
232 BEGIN_BATCH(3); in emit_depthbuffer()
248 BEGIN_BATCH(3); in emit_depthbuffer()
272 BEGIN_BATCH(3); in emit_depthbuffer()
Dgen7_wm_state.c93 BEGIN_BATCH(3); in upload_wm_state()
122 BEGIN_BATCH(2); in upload_ps_state()
128 BEGIN_BATCH(2); in upload_ps_state()
136 BEGIN_BATCH(7); in upload_ps_state()
146 BEGIN_BATCH(7); in upload_ps_state()
212 BEGIN_BATCH(8); in upload_ps_state()
Dintel_batchbuffer.c382 BEGIN_BATCH(4); in intel_emit_depth_stall_flushes()
389 BEGIN_BATCH(4); in intel_emit_depth_stall_flushes()
396 BEGIN_BATCH(4); in intel_emit_depth_stall_flushes()
417 BEGIN_BATCH(4); in gen7_emit_vs_workaround_flush()
469 BEGIN_BATCH(4); in intel_emit_post_sync_nonzero_flush()
477 BEGIN_BATCH(4); in intel_emit_post_sync_nonzero_flush()
516 BEGIN_BATCH(4); in intel_batchbuffer_emit_mi_flush()
530 BEGIN_BATCH(4); in intel_batchbuffer_emit_mi_flush()
539 BEGIN_BATCH(1); in intel_batchbuffer_emit_mi_flush()
Dgen7_cc_state.c36 BEGIN_BATCH(2); in upload_cc_state_pointers()
56 BEGIN_BATCH(2); in upload_blend_state_pointer()
76 BEGIN_BATCH(2); in upload_depth_stencil_state_pointer()
Dgen6_gs_state.c39 BEGIN_BATCH(5); in upload_gs_state()
48 BEGIN_BATCH(7); in upload_gs_state()
66 BEGIN_BATCH(7); in upload_gs_state()
Dgen6_vs_state.c147 BEGIN_BATCH(5); in upload_vs_state()
155 BEGIN_BATCH(5); in upload_vs_state()
176 BEGIN_BATCH(6); in upload_vs_state()
218 BEGIN_BATCH(4); in upload_vs_state()
Dgen7_sol_state.c66 BEGIN_BATCH(4); in upload_3dstate_so_buffers()
91 BEGIN_BATCH(4); in upload_3dstate_so_buffers()
161 BEGIN_BATCH(linked_xfb_info->NumOutputs * 2 + 3); in upload_3dstate_so_decl_list()
226 BEGIN_BATCH(3); in upload_3dstate_streamout()
Dbrw_queryobj.c61 BEGIN_BATCH(4); in write_timestamp()
69 BEGIN_BATCH(5); in write_timestamp()
80 BEGIN_BATCH(4); in write_timestamp()
101 BEGIN_BATCH(5); in write_depth_count()
113 BEGIN_BATCH(4); in write_depth_count()
Dgen6_multisample_state.c103 BEGIN_BATCH(len); in gen6_emit_3dstate_multisample()
123 BEGIN_BATCH(2); in gen6_emit_3dstate_sample_mask()
Dgen6_wm_state.c107 BEGIN_BATCH(5); in upload_wm_state()
115 BEGIN_BATCH(5); in upload_wm_state()
210 BEGIN_BATCH(9); in upload_wm_state()
Dgen7_viewport_state.c69 BEGIN_BATCH(2); in gen7_upload_sf_clip_viewport()
90 BEGIN_BATCH(2); in upload_cc_viewport_state_pointer()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_batchbuffer.c382 BEGIN_BATCH(4); in intel_emit_depth_stall_flushes()
389 BEGIN_BATCH(4); in intel_emit_depth_stall_flushes()
396 BEGIN_BATCH(4); in intel_emit_depth_stall_flushes()
417 BEGIN_BATCH(4); in gen7_emit_vs_workaround_flush()
469 BEGIN_BATCH(4); in intel_emit_post_sync_nonzero_flush()
477 BEGIN_BATCH(4); in intel_emit_post_sync_nonzero_flush()
516 BEGIN_BATCH(4); in intel_batchbuffer_emit_mi_flush()
530 BEGIN_BATCH(4); in intel_batchbuffer_emit_mi_flush()
539 BEGIN_BATCH(1); in intel_batchbuffer_emit_mi_flush()
/external/mesa3d/src/mesa/drivers/dri/intel/
Dintel_batchbuffer.c382 BEGIN_BATCH(4); in intel_emit_depth_stall_flushes()
389 BEGIN_BATCH(4); in intel_emit_depth_stall_flushes()
396 BEGIN_BATCH(4); in intel_emit_depth_stall_flushes()
417 BEGIN_BATCH(4); in gen7_emit_vs_workaround_flush()
469 BEGIN_BATCH(4); in intel_emit_post_sync_nonzero_flush()
477 BEGIN_BATCH(4); in intel_emit_post_sync_nonzero_flush()
516 BEGIN_BATCH(4); in intel_batchbuffer_emit_mi_flush()
530 BEGIN_BATCH(4); in intel_batchbuffer_emit_mi_flush()
539 BEGIN_BATCH(1); in intel_batchbuffer_emit_mi_flush()
/external/mesa3d/src/gallium/drivers/i915/
Di915_blit.c74 if (!BEGIN_BATCH(6)) { in i915_fill_blit()
76 assert(BEGIN_BATCH(6)); in i915_fill_blit()
146 if (!BEGIN_BATCH(8)) { in i915_copy_blit()
148 assert(BEGIN_BATCH(8)); in i915_copy_blit()
Di915_clear.c125 if (!BEGIN_BATCH(1 + 2*(7 + 7))) { in i915_clear_emit()
131 assert(BEGIN_BATCH(1 + 2*(7 + 7))); in i915_clear_emit()
176 if (!BEGIN_BATCH(1 + 7 + 7)) { in i915_clear_emit()
182 assert(BEGIN_BATCH(1 + 7 + 7)); in i915_clear_emit()
Di915_prim_vbuf.c468 if (!BEGIN_BATCH(1 + (nr_indices + 1)/2)) { in draw_arrays_fallback()
476 if (!BEGIN_BATCH(1 + (nr_indices + 1)/2)) { in draw_arrays_fallback()
516 if (!BEGIN_BATCH(2)) { in i915_vbuf_render_draw_arrays()
524 if (!BEGIN_BATCH(2)) { in i915_vbuf_render_draw_arrays()
636 if (!BEGIN_BATCH(1 + (nr_indices + 1)/2)) { in i915_vbuf_render_draw_elements()
644 if (!BEGIN_BATCH(1 + (nr_indices + 1)/2)) { in i915_vbuf_render_draw_elements()
Di915_prim_emit.c147 if (!BEGIN_BATCH( 1 + nr * vertex_size / 4)) { in emit_prim()
154 if (!BEGIN_BATCH( 1 + nr * vertex_size / 4)) { in emit_prim()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_blit.c78 BEGIN_BATCH(14); in emit_vtx_state()
168 BEGIN_BATCH(10); in emit_tx_setup()
186 BEGIN_BATCH(10); in emit_tx_setup()
206 BEGIN_BATCH(34); in emit_tx_setup()
278 BEGIN_BATCH(18); in emit_tx_setup()
430 BEGIN_BATCH(14); in emit_draw_packet()
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_ioctl.c103 BEGIN_BATCH(6); in radeonEmitScissor()
114 BEGIN_BATCH(2); in radeonEmitScissor()
137 BEGIN_BATCH(8); in radeonEmitVbufPrim()
156 BEGIN_BATCH(4); in radeonEmitVbufPrim()
291 BEGIN_BATCH(7); in radeonEmitVertexAOS()
322 BEGIN_BATCH(sz+2+(nr * 2)); in radeonEmitAOS()

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