| /external/boringssl/src/ssl/test/runner/poly1305/ |
| D | poly1305_arm.s | 100 BIC $0xfc000000, R0, R0
101 BIC $0xfc000000, g, g
103 BIC $0xfc000000, R11, R11
104 BIC $0xfc000000, R12, R12
155 BIC $0xfc000000, g, g
156 BIC $0xfc000000, R4, R4
165 BIC $0xfc000000, R0, R0
166 BIC $0xfc000000, R6, R6
174 BIC $0xfc000000, g, R5
175 BIC $0xfc000000, R2, R7
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | arm-abi-attr.ll | 13 ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC
|
| /external/tremolo/Tremolo/ |
| D | bitwiseARM.s | 199 BIC r3,r3,#3 @ r3 = Pointer to start (word)
224 BIC r2,r3,#3 @ r2 = b->headptr (word)
327 BIC r2,r6,#3 @ r2 = word ptr
364 BIC r2,r6,#3 @ r2 = word ptr
|
| D | dpen.s | 144 BIC r10,r10,#0x80 @ r3 = next &= ~0x80
163 BIC r7, r7, #0x8000 @ r7 = chase
204 BIC r10,r10,#0x8000 @ r3 = next &= ~0x8000
221 BIC r7, r7, #0x80000000 @ r7 = chase
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 498 BIC = AND | NOT, enumerator
530 BIC_w = LogicalShiftedFixed | BIC,
531 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
|
| D | macro-assembler-arm64-inl.h | 76 LogicalMacro(rd, rn, operand, BIC); in Bic()
|
| D | assembler-arm64.cc | 1208 Logical(rd, rn, operand, BIC); in bic()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 138 // ADD(S)rr,SUB(S)rr,AND(S)rr,BIC(S)rr,EONrr,EORrr,ORNrr,ORRrr
152 // ADD(S)rs,SUB(S)rs,AND(S)rs,BIC(S)rs,EONrs,EORrs,ORNrs,ORRrs
369 // BIC,ORR V,#imm are WriteV
409 // AND,BIC,CMTST,EOR,ORN,ORR
|
| D | AArch64InstrInfo.td | 856 defm BIC : LogicalReg<0b00, 1, "bic",
2948 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
4247 // AdvSIMD BIC
4248 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
|
| /external/v8/src/arm/ |
| D | constants-arm.h | 155 BIC = 14 << 21, // Bit Clear. enumerator
|
| D | disasm-arm.cc | 932 case BIC: { in DecodeType01()
|
| D | assembler-arm.cc | 1043 alu_insn == BIC) { in fits_shifter()
1565 addrmod1(cond | BIC | s, src1, dst, src2); in bic()
|
| D | simulator-arm.cc | 2520 case BIC: { in DecodeType01()
|
| /external/vixl/src/vixl/a64/ |
| D | constants-a64.h | 525 BIC = AND | NOT, enumerator
557 BIC_w = LogicalShiftedFixed | BIC,
558 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
|
| D | macro-assembler-a64.cc | 660 LogicalMacro(rd, rn, operand, BIC); in Bic()
|
| D | assembler-a64.cc | 1011 Logical(rd, rn, operand, BIC); in bic()
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 166 ### BIC ### subsection
1489 ### BIC ### subsection
1498 ### BIC ### subsection
|
| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 817 // BIC
823 BIC r0, r1, r0 // Must use wide encoding as not flag-setting
|
| D | basic-arm-instructions.s | 485 @ BIC
|
| D | basic-thumb2-instructions.s | 345 @ BIC
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleSwift.td | 128 // AND,BIC,EOR,ORN,ORR
|
| D | ARMInstrThumb.td | 942 // BIC register
|
| D | ARMInstrInfo.td | 3702 defm BIC : AsI1_bin_irs<0b1110, "bic",
5656 // Same for AND <--> BIC
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 207 # BIC
|
| D | basic-arm-instructions.txt | 285 # BIC
|