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Searched refs:DestVT (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
133 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
135 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
940 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPExt() local
942 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1014 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in selectFPTrunc() local
1016 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
898 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPExt() local
900 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in SelectFPExt()
916 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectFPTrunc() local
918 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in SelectFPTrunc()
1161 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1165 if (DestVT != MVT::i16 && DestVT != MVT::i8) in SelectBinaryIntOp()
1333 MVT DestVT = VA.getLocVT(); in processCallArgs() local
1335 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in processCallArgs()
1337 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false)) in processCallArgs()
[all …]
DPPCISelLowering.cpp6760 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
6761 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
6762 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
6770 EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
6771 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
6772 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
6780 SDLoc dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp() argument
6781 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
6782 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, in BuildIntrinsicOp()
/external/llvm/utils/TableGen/
DCallingConvEmitter.cpp223 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
224 O << IndentStr << "LocVT = " << getEnumName(DestVT) <<";\n"; in EmitAction()
225 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
237 MVT::SimpleValueType DestVT = getValueType(DestTy); in EmitAction() local
238 O << IndentStr << "LocVT = " << getEnumName(DestVT) << ";\n"; in EmitAction()
239 if (MVT(DestVT).isFloatingPoint()) { in EmitAction()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp189 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
190 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2720 MVT DestVT; in selectFPToInt() local
2721 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector()) in selectFPToInt()
2735 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2737 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2740 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2742 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2745 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass); in selectFPToInt()
2753 MVT DestVT; in selectIntToFP() local
[all …]
DAArch64ISelLowering.cpp4917 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
4924 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4939 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4945 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4950 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4953 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
4957 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
1746 EVT DestVT = TLI.getValueType(DL, I->getType(), true); in SelectBinaryIntOp() local
1750 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) in SelectBinaryIntOp()
1955 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1956 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); in ProcessCallArgs()
1958 ArgVT = DestVT; in ProcessCallArgs()
1964 MVT DestVT = VA.getLocVT(); in ProcessCallArgs() local
1965 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true); in ProcessCallArgs()
1967 ArgVT = DestVT; in ProcessCallArgs()
2042 MVT DestVT = RVLocs[0].getValVT(); in FinishCall() local
[all …]
DARMISelLowering.cpp5657 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts); in ReconstructShuffle() local
5665 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5681 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5687 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5692 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5695 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5698 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
141 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
143 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
145 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
1120 EVT DestVT = Node->getValueType(0); in LegalizeLoadOps() local
1121 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) { in LegalizeLoadOps()
1147 EVT IDestVT = DestVT.changeTypeToInteger(); in LegalizeLoadOps()
1153 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result); in LegalizeLoadOps()
1923 EVT DestVT, in EmitStackConvert() argument
1937 unsigned DestSize = DestVT.getSizeInBits(); in EmitStackConvert()
[all …]
DSelectionDAGBuilder.cpp2411 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitICmp() local
2413 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode)); in visitICmp()
2431 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitFCmp() local
2433 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition)); in visitFCmp()
2545 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitTrunc() local
2547 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N)); in visitTrunc()
2554 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitZExt() local
2556 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N)); in visitZExt()
2563 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), in visitSExt() local
2565 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N)); in visitSExt()
[all …]
DLegalizeTypes.cpp927 EVT DestVT) { in CreateStackStoreLoad() argument
931 SDValue StackPtr = DAG.CreateStackTemporary(Op.getValueType(), DestVT); in CreateStackStoreLoad()
936 return DAG.getLoad(DestVT, dl, Store, StackPtr, MachinePointerInfo(), in CreateStackStoreLoad()
DLegalizeVectorTypes.cpp246 EVT DestVT = N->getValueType(0).getVectorElementType(); in ScalarizeVecRes_UnaryOp() local
265 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op); in ScalarizeVecRes_UnaryOp()
1215 EVT DestVT = N->getValueType(0); in SplitVecRes_ExtendOp() local
1217 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT); in SplitVecRes_ExtendOp()
1234 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) { in SplitVecRes_ExtendOp()
DLegalizeTypes.h172 SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp1070 MVT DestVT = TLI->getRegisterType(NewVT); in getVectorTypeBreakdownMVT() local
1071 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1072 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1073 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdownMVT()
1434 MVT DestVT = getRegisterType(Context, NewVT); in getVectorTypeBreakdown() local
1435 RegisterVT = DestVT; in getVectorTypeBreakdown()
1442 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1443 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); in getVectorTypeBreakdown()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp1230 EVT DestVT = ASC->getValueType(0); in SelectAddrSpaceCast() local
1234 unsigned DestSize = DestVT.getSizeInBits(); in SelectAddrSpaceCast()
1241 DestVT, in SelectAddrSpaceCast()
1268 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode(); in SelectAddrSpaceCast()
DAMDGPUISelLowering.cpp548 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const { in isNarrowingProfitable()
555 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32; in isNarrowingProfitable()
2191 EVT DestVT = Op.getValueType(); in LowerUINT_TO_FP() local
2192 if (DestVT == MVT::f64) in LowerUINT_TO_FP()
2195 assert(DestVT == MVT::f32); in LowerUINT_TO_FP()
/external/llvm/include/llvm/Target/
DTargetLowering.h1385 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) { in AddPromotedToType() argument
1386 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy; in AddPromotedToType()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp12721 MVT DestVT = Op.getSimpleValueType(); in LowerUINT_TO_FP_i32() local
12723 if (DestVT.bitsLT(MVT::f64)) in LowerUINT_TO_FP_i32()
12724 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, in LowerUINT_TO_FP_i32()
12726 if (DestVT.bitsGT(MVT::f64)) in LowerUINT_TO_FP_i32()
12727 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); in LowerUINT_TO_FP_i32()