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Searched refs:FPRegs (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/Sparc/
DSparcInstrVIS.td87 def FZEROS : VISInstD<0b001100001, "fzeros", FPRegs>;
89 def FONES : VISInstD<0b001111111, "fones", FPRegs>;
91 def FSRC1S : VISInst1<0b001110101, "fsrc1s", FPRegs>;
93 def FSRC2S : VISInst2<0b001111001, "fsrc2s", FPRegs>;
95 def FNOT1S : VISInst1<0b001101011, "fnot1s", FPRegs>;
97 def FNOT2S : VISInst2<0b001100111, "fnot2s", FPRegs>;
99 def FORS : VISInst<0b001111101, "fors", FPRegs>;
101 def FNORS : VISInst<0b001100011, "fnors", FPRegs>;
103 def FANDS : VISInst<0b001110001, "fands", FPRegs>;
105 def FNANDS : VISInst<0b001101111, "fnands", FPRegs>;
[all …]
DSparcInstrInfo.td385 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
408 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
435 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
436 def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32>,
476 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
477 def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>,
923 (outs FPRegs:$rd), (ins FPRegs:$rs2),
925 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
927 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
929 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
[all …]
DSparcInstr64Bit.td330 def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
331 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
404 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
408 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
412 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2),
433 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
435 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>;
447 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
449 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>;
DSparcInstrAliases.td33 (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
56 (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
445 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
450 def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
DSparcRegisterInfo.td290 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp1320 SmallVector<CalleeSavedInfo, 18> FPRegs; in processFunctionBeforeFrameFinalized() local
1344 FPRegs.push_back(CSI[i]); in processFunctionBeforeFrameFinalized()
1382 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { in processFunctionBeforeFrameFinalized()
1383 int FI = FPRegs[i].getFrameIdx(); in processFunctionBeforeFrameFinalized()
/external/llvm/docs/
DWritingAnLLVMBackend.rst531 ``FPRegs``, ``DFPRegs``, and ``IntRegs``. For all three register classes, the
532 first argument defines the namespace with the string "``SP``". ``FPRegs``
540 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>;