Searched refs:IsThumb2 (Results 1 – 7 of 7) sorted by relevance
/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 833 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU]> { 843 Requires<[IsThumb2]>, Sched<[WriteALU, ReadALU, ReadALU]> { 857 Requires<[IsThumb2]>, Sched<[WriteALUsi, ReadALU]> { 1127 Requires<[IsThumb2]> { 1144 Requires<[HasT2ExtractPack, IsThumb2]> { 1160 Requires<[IsThumb2, HasT2ExtractPack]> { 1178 Requires<[HasT2ExtractPack, IsThumb2]> { 1191 Requires<[HasT2ExtractPack, IsThumb2]> { 1678 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>; 1679 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; [all …]
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D | ARMISelDAGToDAG.cpp | 3564 bool IsThumb2 = Subtarget->isThumb2(); in SelectReadRegister() local 3578 Opcode = IsThumb2 ? ARM::t2MRC : ARM::MRC; in SelectReadRegister() 3583 Opcode = IsThumb2 ? ARM::t2MRRC : ARM::MRRC; in SelectReadRegister() 3600 return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSbanked : ARM::MRSbanked, in SelectReadRegister() 3649 return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRS_AR : ARM::MRS, DL, in SelectReadRegister() 3656 return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MRSsys_AR : ARM::MRSsys, in SelectReadRegister() 3669 bool IsThumb2 = Subtarget->isThumb2(); in SelectWriteRegister() local 3682 Opcode = IsThumb2 ? ARM::t2MCR : ARM::MCR; in SelectWriteRegister() 3687 Opcode = IsThumb2 ? ARM::t2MCRR : ARM::MCRR; in SelectWriteRegister() 3705 return CurDAG->getMachineNode(IsThumb2 ? ARM::t2MSRbanked : ARM::MSRbanked, in SelectWriteRegister() [all …]
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D | ARMInstrFormats.td | 257 : InstAlias<Asm, Result, Emit>, Requires<[IsThumb2]>; 358 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>; 396 list<Predicate> Predicates = [IsThumb2]; 1188 list<Predicate> Predicates = [IsThumb2]; 1209 list<Predicate> Predicates = [IsThumb2]; 1222 list<Predicate> Predicates = [IsThumb2]; 1306 : T2I <oops, iops, NoItinerary, opcstr, asm, pattern>, Requires<[IsThumb2]> { 1325 list<Predicate> Predicates = [IsThumb2]; 1358 list<Predicate> Predicates = [IsThumb2]; 1394 list<Predicate> Predicates = [IsThumb2, HasV6T2]; [all …]
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D | ARMISelLowering.cpp | 7459 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) { in getLdOpcode() argument 7467 if (IsThumb2) in getLdOpcode() 7478 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) { in getStOpcode() argument 7486 if (IsThumb2) in getStOpcode() 7500 unsigned AddrOut, bool IsThumb1, bool IsThumb2) { in emitPostLd() argument 7501 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2); in emitPostLd() 7516 } else if (IsThumb2) { in emitPostLd() 7532 unsigned AddrOut, bool IsThumb1, bool IsThumb2) { in emitPostSt() argument 7533 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2); in emitPostSt() 7547 } else if (IsThumb2) { in emitPostSt() [all …]
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D | ARMInstrVFP.td | 936 Requires<[IsThumb2]>; 942 Requires<[IsThumb2]>;
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D | ARMInstrThumb.td | 291 let Predicates = [IsThumb2, HasV8];
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D | ARMInstrInfo.td | 269 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
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