Home
last modified time | relevance | path

Searched refs:MI (Results 1 – 25 of 670) sorted by relevance

12345678910>>...27

/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp38 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT, in getRegOperandVectorVT() argument
40 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
49 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) { in getZeroExtensionTypes() argument
50 switch (MI->getOpcode()) { in getZeroExtensionTypes()
181 static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) { in getVSHUF64x2FamilyInfo() argument
183 switch (MI->getOpcode()) { in getVSHUF64x2FamilyInfo()
190 VT = getRegOperandVectorVT(MI, MVT::i64, 0); in getVSHUF64x2FamilyInfo()
195 VT = getRegOperandVectorVT(MI, MVT::i32, 0); in getVSHUF64x2FamilyInfo()
207 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, in EmitAnyX86InstComments() argument
213 switch (MI->getOpcode()) { in EmitAnyX86InstComments()
[all …]
DX86ATTInstPrinter.h31 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
36 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
37 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
41 void printInstruction(const MCInst *MI, raw_ostream &OS);
44 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
45 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
46 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
47 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
48 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
49 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
[all …]
DX86IntelInstPrinter.h31 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
35 void printInstruction(const MCInst *MI, raw_ostream &O);
38 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
40 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
41 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O);
42 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
45 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h46 unsigned isLoadFromStackSlot(const MachineInstr *MI,
54 unsigned isStoreToStackSlot(const MachineInstr *MI,
174 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
183 MachineBasicBlock::iterator MI) const override;
186 bool isPredicated(const MachineInstr *MI) const override;
190 bool PredicateInstruction(MachineInstr *MI,
201 bool DefinesPredicate(MachineInstr *MI,
207 bool isPredicable(MachineInstr *MI) const override;
211 bool isSchedulingBoundary(const MachineInstr *MI,
230 bool analyzeCompare(const MachineInstr *MI,
[all …]
DHexagonInstrInfo.cpp176 static inline void parseOperands(const MachineInstr *MI, in parseOperands() argument
181 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in parseOperands()
182 const MachineOperand &MO = MI->getOperand(i); in parseOperands()
233 unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, in isLoadFromStackSlot() argument
235 switch (MI->getOpcode()) { in isLoadFromStackSlot()
242 if (MI->getOperand(2).isFI() && in isLoadFromStackSlot()
243 MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { in isLoadFromStackSlot()
244 FrameIndex = MI->getOperand(2).getIndex(); in isLoadFromStackSlot()
245 return MI->getOperand(0).getReg(); in isLoadFromStackSlot()
258 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, in isStoreToStackSlot() argument
[all …]
DHexagonVLIWPacketizer.cpp125 static MachineBasicBlock::iterator moveInstrOut(MachineInstr *MI, in moveInstrOut() argument
133 MachineBasicBlock &B = *MI->getParent(); in moveInstrOut()
136 assert(MI->isBundledWithPred()); in moveInstrOut()
137 if (MI->isBundledWithSucc()) { in moveInstrOut()
138 MI->clearFlag(MachineInstr::BundledSucc); in moveInstrOut()
139 MI->clearFlag(MachineInstr::BundledPred); in moveInstrOut()
144 MI->unbundleFromPred(); in moveInstrOut()
146 B.splice(InsertPt, &B, MI); in moveInstrOut()
201 auto MI = MB.begin(); in runOnMachineFunction() local
202 while (MI != End) { in runOnMachineFunction()
[all …]
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp51 bool LowerSubregToReg(MachineInstr *MI);
52 bool LowerCopy(MachineInstr *MI);
54 void TransferImplicitDefs(MachineInstr *MI);
68 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument
69 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs()
72 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs()
73 MachineOperand &MO = MI->getOperand(i); in TransferImplicitDefs()
80 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument
81 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg()
82 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
[all …]
DTargetInstrInfo.cpp65 MachineBasicBlock::iterator MI) const { in insertNoop()
121 MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr *MI, in commuteInstructionImpl() argument
125 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstructionImpl()
127 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstructionImpl()
133 assert(findCommutedOpIndices(MI, CommutableOpIdx1, CommutableOpIdx2) && in commuteInstructionImpl()
136 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstructionImpl()
139 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstructionImpl()
140 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstructionImpl()
141 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstructionImpl()
142 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; in commuteInstructionImpl()
[all …]
/external/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp78 void SkipIfDead(MachineInstr &MI);
80 void If(MachineInstr &MI);
81 void Else(MachineInstr &MI);
82 void Break(MachineInstr &MI);
83 void IfBreak(MachineInstr &MI);
84 void ElseBreak(MachineInstr &MI);
85 void Loop(MachineInstr &MI);
86 void EndCf(MachineInstr &MI);
88 void Kill(MachineInstr &MI);
89 void Branch(MachineInstr &MI);
[all …]
DSIInstrInfo.h29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI,
35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI,
68 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
71 MachineInstr *commuteInstructionImpl(MachineInstr *MI,
83 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
99 MachineBasicBlock::iterator MI, DebugLoc DL,
104 MachineBasicBlock::iterator MI,
111 MachineBasicBlock::iterator MI,
117 MachineBasicBlock::iterator MI,
122 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp40 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
41 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
42 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
43 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
44 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
45 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
63 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
64 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
65 !MI.getOperand(0).isTied()) in tieOpsIfNeeded()
66 MI.tieOperands(0, 1); in tieOpsIfNeeded()
[all …]
DSystemZAsmPrinter.cpp31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { in lowerRILow() argument
32 if (MI->isCompare()) in lowerRILow()
34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) { in lowerRIHigh() argument
46 if (MI->isCompare()) in lowerRIHigh()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
[all …]
DSystemZInstrInfo.cpp50 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI, in splitMove() argument
52 MachineBasicBlock *MBB = MI->getParent(); in splitMove()
57 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI); in splitMove()
58 MBB->insert(MI, EarlierMI); in splitMove()
62 MachineOperand &LowRegOp = MI->getOperand(0); in splitMove()
69 MachineOperand &LowOffsetOp = MI->getOperand(2); in splitMove()
83 MI->setDesc(get(LowOpcode)); in splitMove()
87 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const { in splitAdjDynAlloc()
88 MachineBasicBlock *MBB = MI->getParent(); in splitAdjDynAlloc()
91 MachineOperand &OffsetMO = MI->getOperand(2); in splitAdjDynAlloc()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.h29 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
34 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
38 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
41 void printSORegRegOperand(const MCInst *MI, unsigned OpNum,
43 void printSORegImmOperand(const MCInst *MI, unsigned OpNum,
46 void printAddrModeTBB(const MCInst *MI, unsigned OpNum,
48 void printAddrModeTBH(const MCInst *MI, unsigned OpNum,
50 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum,
52 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum,
54 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
[all …]
DARMInstPrinter.cpp69 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
71 unsigned Opcode = MI->getOpcode(); in printInst()
79 switch (MI->getOperand(0).getImm()) { in printInst()
102 printInstruction(MI, STI, O); in printInst()
106 printPredicateOperand(MI, 1, STI, O); in printInst()
115 const MCOperand &Dst = MI->getOperand(0); in printInst()
116 const MCOperand &MO1 = MI->getOperand(1); in printInst()
117 const MCOperand &MO2 = MI->getOperand(2); in printInst()
118 const MCOperand &MO3 = MI->getOperand(3); in printInst()
121 printSBitModifierOperand(MI, 6, STI, O); in printInst()
[all …]
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() argument
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
34 return MI.getOperand(OpNo).getReg() == R; in isReg()
79 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
81 switch (MI->getOpcode()) { in printInst()
91 printSaveRestore(MI, O); in printInst()
96 printSaveRestore(MI, O); in printInst()
101 printSaveRestore(MI, O); in printInst()
106 printSaveRestore(MI, O); in printInst()
112 if (!printAliasInstr(MI, O) && !printAlias(*MI, O)) in printInst()
[all …]
/external/llvm/lib/Target/SystemZ/InstPrinter/
DSystemZInstPrinter.cpp52 void SystemZInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
55 printInstruction(MI, O); in printInst()
64 static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { in printUImmOperand() argument
65 int64_t Value = MI->getOperand(OpNum).getImm(); in printUImmOperand()
71 static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { in printSImmOperand() argument
72 int64_t Value = MI->getOperand(OpNum).getImm(); in printSImmOperand()
77 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum, in printU1ImmOperand() argument
79 printUImmOperand<1>(MI, OpNum, O); in printU1ImmOperand()
82 void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum, in printU2ImmOperand() argument
84 printUImmOperand<2>(MI, OpNum, O); in printU2ImmOperand()
[all …]
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCCodeEmitter.cpp40 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
46 uint64_t getBinaryCodeForInstr(const MCInst &MI,
52 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
60 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
63 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
66 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
69 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
72 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
75 uint64_t getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum,
84 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
[all …]
/external/llvm/lib/Target/AMDGPU/InstPrinter/
DAMDGPUInstPrinter.h29 void printInstruction(const MCInst *MI, raw_ostream &O);
32 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
38 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
40 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
45 void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
[all …]
DAMDGPUInstPrinter.cpp22 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, in printInst() argument
25 printInstruction(MI, OS); in printInst()
30 void AMDGPUInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo, in printU8ImmOperand() argument
32 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
35 void AMDGPUInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo, in printU16ImmOperand() argument
37 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmOperand()
40 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo, in printU32ImmOperand() argument
42 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
45 void AMDGPUInstPrinter::printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, in printU8ImmDecOperand() argument
47 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
[all …]
/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp56 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
59 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
60 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
61 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
62 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
72 printOperand(MI, 0, O); in printInst()
74 printOperand(MI, 1, O); in printInst()
82 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
83 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
85 printOperand(MI, 0, O); in printInst()
[all …]
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp48 uint64_t getBinaryCodeForInstr(const MCInst &MI,
54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
62 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
68 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
74 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
80 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp51 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
54 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
57 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo,
60 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo,
63 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
66 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
69 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
72 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo,
75 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo,
78 unsigned getSPE2DisEncoding(const MCInst &MI, unsigned OpNo,
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp68 uint64_t getBinaryCodeForInstr(const MCInst &MI,
74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp148 encodeInstruction(const MCInst &MI, raw_ostream &OS, in encodeInstruction() argument
157 MCInst TmpInst = MI; in encodeInstruction()
158 switch (MI.getOpcode()) { in encodeInstruction()
221 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValue() argument
225 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
244 getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, in getBranchTarget7OpValueMM() argument
248 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTarget7OpValueMM()
266 getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValueMMPC10() argument
270 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueMMPC10()
288 getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, in getBranchTargetOpValueMM() argument
[all …]

12345678910>>...27