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Searched refs:OUT_BATCH (Results 1 – 25 of 59) sorted by relevance

123

/external/mesa3d/src/mesa/drivers/dri/i965/
Dgen7_disable.c38 OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2)); in disable_stages()
39 OUT_BATCH(0); in disable_stages()
40 OUT_BATCH(0); in disable_stages()
41 OUT_BATCH(0); in disable_stages()
42 OUT_BATCH(0); in disable_stages()
43 OUT_BATCH(0); in disable_stages()
44 OUT_BATCH(0); in disable_stages()
48 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); in disable_stages()
49 OUT_BATCH(0); /* prog_bo */ in disable_stages()
50 OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) | in disable_stages()
[all …]
Dgen6_blorp.cpp99 OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16); in gen6_blorp_emit_batch_head()
124 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); in gen6_blorp_emit_state_base_address()
125 OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */ in gen6_blorp_emit_state_base_address()
131 OUT_BATCH(1); /* IndirectObjectBaseAddress */ in gen6_blorp_emit_state_base_address()
136 OUT_BATCH(1); /* InstructionBaseAddress */ in gen6_blorp_emit_state_base_address()
138 OUT_BATCH(1); /* GeneralStateUpperBound */ in gen6_blorp_emit_state_base_address()
144 OUT_BATCH(0xfffff001); in gen6_blorp_emit_state_base_address()
145 OUT_BATCH(1); /* IndirectObjectUpperBound*/ in gen6_blorp_emit_state_base_address()
146 OUT_BATCH(1); /* InstructionAccessUpperBound */ in gen6_blorp_emit_state_base_address()
214 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2)); in gen6_blorp_emit_vertices()
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Dgen7_blorp.cpp73 OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2)); in gen7_blorp_emit_blend_state_pointer()
74 OUT_BATCH(cc_blend_state_offset | 1); in gen7_blorp_emit_blend_state_pointer()
88 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); in gen7_blorp_emit_cc_state_pointer()
89 OUT_BATCH(cc_state_offset | 1); in gen7_blorp_emit_cc_state_pointer()
108 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2)); in gen7_blorp_emit_cc_viewport()
109 OUT_BATCH(cc_vp_offset); in gen7_blorp_emit_cc_viewport()
126 OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2)); in gen7_blorp_emit_depth_stencil_state_pointers()
127 OUT_BATCH(depthstencil_offset | 1); in gen7_blorp_emit_depth_stencil_state_pointers()
289 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2)); in gen7_blorp_emit_hs_disable()
290 OUT_BATCH(0); in gen7_blorp_emit_hs_disable()
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Dbrw_misc_state.c52 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); in upload_drawing_rect()
53 OUT_BATCH(0); /* xmin, ymin */ in upload_drawing_rect()
54 OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) | in upload_drawing_rect()
56 OUT_BATCH(0); in upload_drawing_rect()
81 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2)); in upload_binding_table_pointers()
82 OUT_BATCH(brw->vs.bind_bo_offset); in upload_binding_table_pointers()
83 OUT_BATCH(0); /* gs */ in upload_binding_table_pointers()
84 OUT_BATCH(0); /* clip */ in upload_binding_table_pointers()
85 OUT_BATCH(0); /* sf */ in upload_binding_table_pointers()
86 OUT_BATCH(brw->wm.bind_bo_offset); in upload_binding_table_pointers()
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Dgen7_vs_state.c44 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2)); in upload_vs_state()
45 OUT_BATCH(brw->vs.bind_bo_offset); in upload_vs_state()
50 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2)); in upload_vs_state()
51 OUT_BATCH(brw->sampler.offset); in upload_vs_state()
57 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); in upload_vs_state()
58 OUT_BATCH(0); in upload_vs_state()
59 OUT_BATCH(0); in upload_vs_state()
60 OUT_BATCH(0); in upload_vs_state()
61 OUT_BATCH(0); in upload_vs_state()
62 OUT_BATCH(0); in upload_vs_state()
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Dgen6_gs_state.c40 OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (5 - 2)); in upload_gs_state()
41 OUT_BATCH(0); in upload_gs_state()
42 OUT_BATCH(0); in upload_gs_state()
43 OUT_BATCH(0); in upload_gs_state()
44 OUT_BATCH(0); in upload_gs_state()
49 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); in upload_gs_state()
50 OUT_BATCH(brw->gs.prog_offset); in upload_gs_state()
51 OUT_BATCH(GEN6_GS_SPF_MODE | GEN6_GS_VECTOR_MASK_ENABLE); in upload_gs_state()
52 OUT_BATCH(0); /* no scratch space */ in upload_gs_state()
53 OUT_BATCH((2 << GEN6_GS_DISPATCH_START_GRF_SHIFT) | in upload_gs_state()
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Dgen7_wm_state.c94 OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2)); in upload_wm_state()
95 OUT_BATCH(dw1); in upload_wm_state()
96 OUT_BATCH(dw2); in upload_wm_state()
123 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2)); in upload_ps_state()
124 OUT_BATCH(brw->wm.bind_bo_offset); in upload_ps_state()
129 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2)); in upload_ps_state()
130 OUT_BATCH(brw->sampler.offset); in upload_ps_state()
137 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2)); in upload_ps_state()
138 OUT_BATCH(0); in upload_ps_state()
139 OUT_BATCH(0); in upload_ps_state()
[all …]
Dgen7_misc_state.c147 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); in emit_depthbuffer()
148 OUT_BATCH(dw1); in emit_depthbuffer()
149 OUT_BATCH(0); in emit_depthbuffer()
150 OUT_BATCH(dw3); in emit_depthbuffer()
151 OUT_BATCH(0); in emit_depthbuffer()
152 OUT_BATCH(tile_x | (tile_y << 16)); in emit_depthbuffer()
153 OUT_BATCH(0); in emit_depthbuffer()
191 OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); in emit_depthbuffer()
192 OUT_BATCH(((region->pitch * region->cpp) - 1) | in emit_depthbuffer()
201 OUT_BATCH((((drb->Base.Base.Width + tile_x) - 1) << 4) | in emit_depthbuffer()
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Dintel_batchbuffer.c383 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
384 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
385 OUT_BATCH(0); /* address */ in intel_emit_depth_stall_flushes()
386 OUT_BATCH(0); /* write data */ in intel_emit_depth_stall_flushes()
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
391 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH); in intel_emit_depth_stall_flushes()
392 OUT_BATCH(0); /* address */ in intel_emit_depth_stall_flushes()
393 OUT_BATCH(0); /* write data */ in intel_emit_depth_stall_flushes()
397 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
398 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
[all …]
Dgen6_vs_state.c148 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2)); in upload_vs_state()
149 OUT_BATCH(0); in upload_vs_state()
150 OUT_BATCH(0); in upload_vs_state()
151 OUT_BATCH(0); in upload_vs_state()
152 OUT_BATCH(0); in upload_vs_state()
156 OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | in upload_vs_state()
162 OUT_BATCH(brw->vs.push_const_offset + in upload_vs_state()
164 OUT_BATCH(0); in upload_vs_state()
165 OUT_BATCH(0); in upload_vs_state()
166 OUT_BATCH(0); in upload_vs_state()
[all …]
Dgen6_wm_state.c108 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2)); in upload_wm_state()
109 OUT_BATCH(0); in upload_wm_state()
110 OUT_BATCH(0); in upload_wm_state()
111 OUT_BATCH(0); in upload_wm_state()
112 OUT_BATCH(0); in upload_wm_state()
116 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | in upload_wm_state()
122 OUT_BATCH(brw->wm.push_const_offset + in upload_wm_state()
125 OUT_BATCH(0); in upload_wm_state()
126 OUT_BATCH(0); in upload_wm_state()
127 OUT_BATCH(0); in upload_wm_state()
[all …]
Dgen7_urb.c58 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2)); in gen7_allocate_push_constants()
59 OUT_BATCH(8); in gen7_allocate_push_constants()
63 OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2)); in gen7_allocate_push_constants()
64 OUT_BATCH(8 | 8 << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT); in gen7_allocate_push_constants()
114 OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2)); in gen7_emit_urb_state()
115 OUT_BATCH(nr_vs_entries | in gen7_emit_urb_state()
122 OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2)); in gen7_emit_urb_state()
123 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | in gen7_emit_urb_state()
128 OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2)); in gen7_emit_urb_state()
129 OUT_BATCH((0 << GEN7_URB_ENTRY_SIZE_SHIFT) | in gen7_emit_urb_state()
[all …]
Dintel_blit.c200 OUT_BATCH(CMD); in intelEmitCopyBlit()
201 OUT_BATCH(BR13 | (uint16_t)dst_pitch); in intelEmitCopyBlit()
202 OUT_BATCH((dst_y << 16) | dst_x); in intelEmitCopyBlit()
203 OUT_BATCH((dst_y2 << 16) | dst_x2); in intelEmitCopyBlit()
207 OUT_BATCH((src_y << 16) | src_x); in intelEmitCopyBlit()
208 OUT_BATCH((uint16_t)src_pitch); in intelEmitCopyBlit()
374 OUT_BATCH(CMD); in intelClearWithBlit()
375 OUT_BATCH(BR13); in intelClearWithBlit()
376 OUT_BATCH((y1 << 16) | x1); in intelClearWithBlit()
377 OUT_BATCH((y2 << 16) | x2); in intelClearWithBlit()
[all …]
Dgen7_sol_state.c67 OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2)); in upload_3dstate_so_buffers()
68 OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT)); in upload_3dstate_so_buffers()
69 OUT_BATCH(0); in upload_3dstate_so_buffers()
70 OUT_BATCH(0); in upload_3dstate_so_buffers()
92 OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2)); in upload_3dstate_so_buffers()
93 OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) | stride); in upload_3dstate_so_buffers()
162 OUT_BATCH(_3DSTATE_SO_DECL_LIST << 16 | in upload_3dstate_so_decl_list()
165 OUT_BATCH((buffer_mask << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT) | in upload_3dstate_so_decl_list()
170 OUT_BATCH((linked_xfb_info->NumOutputs << SO_NUM_ENTRIES_0_SHIFT) | in upload_3dstate_so_decl_list()
176 OUT_BATCH(so_decl[i]); in upload_3dstate_so_decl_list()
[all …]
/external/mesa3d/src/gallium/drivers/i915/
Di915_clear.c134 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); in i915_clear_emit()
136 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
137 OUT_BATCH(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT); in i915_clear_emit()
139 OUT_BATCH(clear_color); in i915_clear_emit()
140 OUT_BATCH(clear_depth); in i915_clear_emit()
142 OUT_BATCH(clear_color8888); in i915_clear_emit()
144 OUT_BATCH(clear_stencil); in i915_clear_emit()
146 OUT_BATCH(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5); in i915_clear_emit()
154 OUT_BATCH(_3DSTATE_CLEAR_PARAMETERS); in i915_clear_emit()
155 OUT_BATCH((clear_params & ~CLEARPARAM_WRITE_COLOR) | in i915_clear_emit()
[all …]
Di915_state_emit.c68 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE); in emit_flush()
70 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE); in emit_flush()
143 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | in emit_immediate()
151 OUT_BATCH(0); in emit_immediate()
169 OUT_BATCH(imm); in emit_immediate()
171 OUT_BATCH(i915->current.immediate[i]); in emit_immediate()
189 OUT_BATCH(i915->current.dynamic[i]); in emit_dynamic()
221 OUT_BATCH(_3DSTATE_BUF_INFO_CMD); in emit_static()
222 OUT_BATCH(i915->current.cbuf_flags); in emit_static()
231 OUT_BATCH(_3DSTATE_BUF_INFO_CMD); in emit_static()
[all …]
Di915_blit.c78 OUT_BATCH(CMD); in i915_fill_blit()
79 OUT_BATCH(BR13); in i915_fill_blit()
80 OUT_BATCH((y << 16) | x); in i915_fill_blit()
81 OUT_BATCH(((y + h) << 16) | (x + w)); in i915_fill_blit()
83 OUT_BATCH(color); in i915_fill_blit()
150 OUT_BATCH(CMD); in i915_copy_blit()
151 OUT_BATCH(BR13); in i915_copy_blit()
152 OUT_BATCH((dst_y << 16) | dst_x); in i915_copy_blit()
153 OUT_BATCH((dst_y2 << 16) | dst_x2); in i915_copy_blit()
155 OUT_BATCH((src_y << 16) | src_x); in i915_copy_blit()
[all …]
Di915_prim_emit.c83 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
87 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
88 OUT_BATCH( fui(attrib[1]) ); in emit_hw_vertex()
92 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
93 OUT_BATCH( fui(attrib[1]) ); in emit_hw_vertex()
94 OUT_BATCH( fui(attrib[2]) ); in emit_hw_vertex()
98 OUT_BATCH( fui(attrib[0]) ); in emit_hw_vertex()
99 OUT_BATCH( fui(attrib[1]) ); in emit_hw_vertex()
100 OUT_BATCH( fui(attrib[2]) ); in emit_hw_vertex()
101 OUT_BATCH( fui(attrib[3]) ); in emit_hw_vertex()
[all …]
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_batchbuffer.c383 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
384 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
385 OUT_BATCH(0); /* address */ in intel_emit_depth_stall_flushes()
386 OUT_BATCH(0); /* write data */ in intel_emit_depth_stall_flushes()
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
391 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH); in intel_emit_depth_stall_flushes()
392 OUT_BATCH(0); /* address */ in intel_emit_depth_stall_flushes()
393 OUT_BATCH(0); /* write data */ in intel_emit_depth_stall_flushes()
397 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
398 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
[all …]
Di830_vtbl.c306 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in i830_emit_invarient_state()
307 OUT_BATCH(0); in i830_emit_invarient_state()
309 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in i830_emit_invarient_state()
310 OUT_BATCH(0); in i830_emit_invarient_state()
312 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in i830_emit_invarient_state()
313 OUT_BATCH(0); in i830_emit_invarient_state()
315 OUT_BATCH(_3DSTATE_FOG_MODE_CMD); in i830_emit_invarient_state()
316 OUT_BATCH(FOGFUNC_ENABLE | in i830_emit_invarient_state()
318 OUT_BATCH(0); in i830_emit_invarient_state()
319 OUT_BATCH(0); in i830_emit_invarient_state()
[all …]
Di915_vtbl.c182 OUT_BATCH(_3DSTATE_AA_CMD | in i915_emit_invarient_state()
187 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); in i915_emit_invarient_state()
188 OUT_BATCH(0); in i915_emit_invarient_state()
190 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); in i915_emit_invarient_state()
191 OUT_BATCH(0); in i915_emit_invarient_state()
193 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); in i915_emit_invarient_state()
194 OUT_BATCH(0); in i915_emit_invarient_state()
197 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS | in i915_emit_invarient_state()
206 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0)); in i915_emit_invarient_state()
207 OUT_BATCH(0); in i915_emit_invarient_state()
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Dintel_blit.c200 OUT_BATCH(CMD); in intelEmitCopyBlit()
201 OUT_BATCH(BR13 | (uint16_t)dst_pitch); in intelEmitCopyBlit()
202 OUT_BATCH((dst_y << 16) | dst_x); in intelEmitCopyBlit()
203 OUT_BATCH((dst_y2 << 16) | dst_x2); in intelEmitCopyBlit()
207 OUT_BATCH((src_y << 16) | src_x); in intelEmitCopyBlit()
208 OUT_BATCH((uint16_t)src_pitch); in intelEmitCopyBlit()
374 OUT_BATCH(CMD); in intelClearWithBlit()
375 OUT_BATCH(BR13); in intelClearWithBlit()
376 OUT_BATCH((y1 << 16) | x1); in intelClearWithBlit()
377 OUT_BATCH((y2 << 16) | x2); in intelClearWithBlit()
[all …]
/external/mesa3d/src/mesa/drivers/dri/intel/
Dintel_batchbuffer.c383 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
384 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
385 OUT_BATCH(0); /* address */ in intel_emit_depth_stall_flushes()
386 OUT_BATCH(0); /* write data */ in intel_emit_depth_stall_flushes()
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
391 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH); in intel_emit_depth_stall_flushes()
392 OUT_BATCH(0); /* address */ in intel_emit_depth_stall_flushes()
393 OUT_BATCH(0); /* write data */ in intel_emit_depth_stall_flushes()
397 OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2)); in intel_emit_depth_stall_flushes()
398 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL); in intel_emit_depth_stall_flushes()
[all …]
Dintel_blit.c200 OUT_BATCH(CMD); in intelEmitCopyBlit()
201 OUT_BATCH(BR13 | (uint16_t)dst_pitch); in intelEmitCopyBlit()
202 OUT_BATCH((dst_y << 16) | dst_x); in intelEmitCopyBlit()
203 OUT_BATCH((dst_y2 << 16) | dst_x2); in intelEmitCopyBlit()
207 OUT_BATCH((src_y << 16) | src_x); in intelEmitCopyBlit()
208 OUT_BATCH((uint16_t)src_pitch); in intelEmitCopyBlit()
374 OUT_BATCH(CMD); in intelClearWithBlit()
375 OUT_BATCH(BR13); in intelClearWithBlit()
376 OUT_BATCH((y1 << 16) | x1); in intelClearWithBlit()
377 OUT_BATCH((y2 << 16) | x2); in intelClearWithBlit()
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/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_ioctl.c104 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
105 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE); in radeonEmitScissor()
106 OUT_BATCH(CP_PACKET0(RADEON_RE_TOP_LEFT, 0)); in radeonEmitScissor()
107 OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) | in radeonEmitScissor()
109 OUT_BATCH(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0)); in radeonEmitScissor()
110 OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2) << 16) | in radeonEmitScissor()
115 OUT_BATCH(CP_PACKET0(RADEON_PP_CNTL, 0)); in radeonEmitScissor()
116 OUT_BATCH(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE); in radeonEmitScissor()
139 OUT_BATCH(rmesa->ioctl.vertex_offset); in radeonEmitVbufPrim()
141 OUT_BATCH(vertex_nr); in radeonEmitVbufPrim()
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