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Searched refs:Rt2 (Results 1 – 23 of 23) sorted by relevance

/external/llvm/test/MC/AArch64/
Darm64-diags.s155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-unpredictable.txt46 # Unpredictable if Rt == Rt2 on a load.
67 # Unpredictable if Rt == Rt2 on a load.
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1086 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodeExclusiveLdStInstruction() local
1140 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1149 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodeExclusiveLdStInstruction()
1158 Rt == Rt2) in DecodeExclusiveLdStInstruction()
1169 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodePairLdStInstruction() local
1228 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1241 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1252 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1263 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
1274 DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder); in DecodePairLdStInstruction()
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7-xfail.txt9 # Rt == Rt2 is UNPREDICTABLE
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1623 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction() local
1647 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1651 if (Rt2 == 15) in DecodeAddrMode3Instruction()
1670 if (Rt2 == 15) in DecodeAddrMode3Instruction()
1676 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
1680 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
4859 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVSRR() local
4864 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVSRR()
4873 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) in DecodeVMOVSRR()
4885 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVRRS() local
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/external/llvm/lib/Target/ARM/
DARMInstrVFP.td850 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
851 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
856 bits<4> Rt2;
862 let Inst{19-16} = Rt2;
872 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
877 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
878 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
882 bits<4> Rt2;
888 let Inst{19-16} = Rt2;
903 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
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DARMInstrThumb2.td1280 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1282 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>;
1451 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1452 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>;
1559 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1561 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
1566 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1568 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1573 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1574 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
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DARMInstrInfo.td2509 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2510 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2625 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2628 "ldrd", "\t$Rt, $Rt2, $addr!",
2638 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2641 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2776 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2777 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
2942 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2944 "strd", "\t$Rt, $Rt2, $addr!",
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DARMInstrFormats.td577 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
579 bits<4> Rt2;
587 let Inst{3-0} = Rt2;
1258 bits<4> Rt2;
1268 let Inst{11-8} = Rt2{3-0};
1277 bits<4> Rt2;
1288 let Inst{11-8} = Rt2{3-0};
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td3204 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3206 bits<5> Rt2;
3215 let Inst{14-10} = Rt2;
3226 (outs regtype:$Rt, regtype:$Rt2),
3230 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3231 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3240 (ins regtype:$Rt, regtype:$Rt2,
3245 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3246 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3253 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
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/external/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp3485 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
3490 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
3502 unsigned Rt2 = Inst.getOperand(1).getReg(); in validateInstruction() local
3503 if (Rt == Rt2) in validateInstruction()
3515 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
3516 if (Rt == Rt2) in validateInstruction()
3531 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
3536 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
/external/llvm/test/MC/ARM/
Ddiagnostics.s300 @ Out of order Rt/Rt2 operands for ldrexd/strexd
374 @ Out of order Rt/Rt2 operands for ldrd
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp5903 unsigned Rt2 = MRI->getEncodingValue(Reg2); in ParseInstruction() local
5906 if (Rt + 1 != Rt2 || (Rt & 1)) { in ParseInstruction()
6100 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction() local
6101 if (Rt2 != Rt + 1) in validateInstruction()
6109 if (Rn == Rt || Rn == Rt2) in validateInstruction()
6122 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction() local
6123 if (Rt2 == Rt) in validateInstruction()
6139 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction() local
6140 if (Rt2 != Rt + 1) in validateInstruction()
6149 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg()); in validateInstruction() local
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/external/vixl/src/vixl/a64/
Dassembler-a64.cc1479 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | in LoadStorePair()
1526 Emit(op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | ImmLSPair(offset, size)); in LoadStorePairNonTemporal()
1761 Emit(op | Rs(rs) | Rt(rt) | Rt2(rt2) | RnSP(dst.base())); in stxp()
1771 Emit(op | Rs_mask | Rt(rt) | Rt2(rt2) | RnSP(src.base())); in ldxp()
1829 Emit(op | Rs(rs) | Rt(rt) | Rt2(rt2) | RnSP(dst.base())); in stlxp()
1839 Emit(op | Rs_mask | Rt(rt) | Rt2(rt2) | RnSP(src.base())); in ldaxp()
Dconstants-a64.h55 V_(Rt2, 14, 10, Bits) /* Load/store second register. */ \
Dsimulator-a64.cc1176 unsigned rt2 = instr->Rt2(); in LoadStorePairHelper()
1296 unsigned rt2 = instr->Rt2(); in VisitLoadStoreExclusive()
Ddisasm-a64.cc2878 reg_num = instr->Rt2(); in SubstituteRegisterField()
Dassembler-a64.h3796 static Instr Rt2(CPURegister rt2) { in Rt2() function
/external/v8/src/arm64/
Dconstants-arm64.h127 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
Ddisasm-arm64.cc1291 reg_num = instr->Rt2(); in SubstituteRegisterField()
Dassembler-arm64.h1683 static Instr Rt2(CPURegister rt2) { in Rt2() function
Dassembler-arm64.cc1607 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | in LoadStorePair()
Dsimulator-arm64.cc1689 unsigned rt2 = instr->Rt2(); in LoadStorePairHelper()