| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.memcpy.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-pr…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check…
9 ; SI: ds_read_u8
10 ; SI: ds_read_u8
11 ; SI: ds_read_u8
12 ; SI: ds_read_u8
13 ; SI: ds_read_u8
14 ; SI: ds_read_u8
15 ; SI: ds_read_u8
16 ; SI: ds_read_u8
[all …]
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| D | unaligned-load-store.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
4 ; SI-LABEL: {{^}}unaligned_load_store_i16_local:
5 ; SI: ds_read_u8
6 ; SI: ds_read_u8
7 ; SI: ds_write_b8
8 ; SI: ds_write_b8
9 ; SI: s_endpgm
16 ; SI-LABEL: {{^}}unaligned_load_store_i16_global:
17 ; SI: buffer_load_ubyte
[all …]
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| D | global-extload-i32.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-pre…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-…
6 ; SI: buffer_load_dword v[[LO:[0-9]+]],
7 ; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
8 ; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
17 ; SI: buffer_load_dword [[LOAD:v[0-9]+]],
18 ; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]]
19 ; SI: buffer_store_dwordx2
28 ; SI: buffer_load_dword
29 ; SI: buffer_store_dwordx2
[all …]
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| D | udivrem.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=SI --che…
30 ; SI: v_rcp_iflag_f32_e32 [[RCP:v[0-9]+]]
31 ; SI-DAG: v_mul_hi_u32 [[RCP_HI:v[0-9]+]], [[RCP]]
32 ; SI-DAG: v_mul_lo_i32 [[RCP_LO:v[0-9]+]], [[RCP]]
33 ; SI-DAG: v_sub_i32_e32 [[NEG_RCP_LO:v[0-9]+]], vcc, 0, [[RCP_LO]]
34 ; SI: v_cndmask_b32_e64
35 ; SI: v_mul_hi_u32 [[E:v[0-9]+]], {{v[0-9]+}}, [[RCP]]
36 ; SI-DAG: v_add_i32_e32 [[RCP_A_E:v[0-9]+]], vcc, [[E]], [[RCP]]
37 ; SI-DAG: v_subrev_i32_e32 [[RCP_S_E:v[0-9]+]], vcc, [[E]], [[RCP]]
[all …]
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| D | trunc-store.ll | 1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check…
5 ; SI: buffer_store_byte
6 ; SI: buffer_store_byte
7 ; SI: buffer_store_byte
8 ; SI: buffer_store_byte
9 ; SI: buffer_store_byte
10 ; SI: buffer_store_byte
11 ; SI: buffer_store_byte
12 ; SI: buffer_store_byte
[all …]
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| D | s_movk_i32.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
4 ; SI-LABEL: {{^}}s_movk_i32_k0:
5 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff{{$}}
6 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
7 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, [[LO_S_IMM]], v[[LO_VREG]]
8 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 1, v[[HI_VREG]]
9 ; SI: s_endpgm
17 ; SI-LABEL: {{^}}s_movk_i32_k1:
18 ; SI-DAG: s_movk_i32 [[LO_S_IMM:s[0-9]+]], 0x7fff{{$}}
[all …]
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| D | copy-illegal-type.ll | 1 ; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
5 ; SI: buffer_load_dword [[REG:v[0-9]+]]
6 ; SI: buffer_store_dword [[REG]]
7 ; SI: s_endpgm
15 ; SI: buffer_load_dword [[REG:v[0-9]+]]
16 ; SI: buffer_store_dword [[REG]]
17 ; SI: buffer_store_dword [[REG]]
18 ; SI: s_endpgm
27 ; SI: buffer_load_dword [[REG:v[0-9]+]]
[all …]
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| D | select-vectors.ll | 1 ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-pr…
2 ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check…
9 ; SI: v_cndmask_b32_e32
10 ; SI: v_cndmask_b32_e32
11 ; SI: v_cndmask_b32_e32
12 ; SI: v_cndmask_b32_e32
21 ; SI: v_cndmask_b32_e32
22 ; SI: v_cndmask_b32_e32
23 ; SI: v_cndmask_b32_e32
24 ; SI: v_cndmask_b32_e32
[all …]
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| D | llvm.AMDGPU.class.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
9 ; SI-LABEL: {{^}}test_class_f32:
10 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
11 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
12 ; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
13 ; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[VB]]
14 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc
15 ; SI-NEXT: buffer_store_dword [[RESULT]]
16 ; SI: s_endpgm
24 ; SI-LABEL: {{^}}test_class_fabs_f32:
[all …]
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| D | bswap.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-pr…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check…
13 ; SI: buffer_load_dword [[VAL:v[0-9]+]]
14 ; SI-DAG: v_alignbit_b32 [[TMP0:v[0-9]+]], [[VAL]], [[VAL]], 8
15 ; SI-DAG: v_alignbit_b32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24
16 ; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0xff00ff
17 ; SI: v_bfi_b32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]]
18 ; SI: buffer_store_dword [[RESULT]]
19 ; SI: s_endpgm
28 ; SI-DAG: v_alignbit_b32
[all …]
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| D | cvt_f32_ubyte.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
4 ; SI-LABEL: {{^}}load_i8_to_f32:
5 ; SI: buffer_load_ubyte [[LOADREG:v[0-9]+]],
6 ; SI-NOT: bfe
7 ; SI-NOT: lshr
8 ; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]]
9 ; SI: buffer_store_dword [[CONV]],
17 ; SI-LABEL: {{^}}load_v2i8_to_v2f32:
18 ; SI: buffer_load_ushort [[LOADREG:v[0-9]+]],
[all …]
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| D | llvm.sin.ll | 2 ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-pr…
3 ; RUN: llc -march=amdgcn -mcpu=SI -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-p…
4 ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check…
5 … -mcpu=tonga -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-UNSAFE -che…
13 ; SI: v_mul_f32
14 ; SI: v_fract_f32
15 ; SI: v_sin_f32
16 ; SI-NOT: v_sin_f32
25 ; SI-UNSAFE-NOT: v_add_f32
26 ; SI-UNSAFE: 0x3ef47644
[all …]
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| D | llvm.AMDGPU.bfe.i32.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-pr…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check…
8 ; SI: v_bfe_i32
18 ; SI: v_bfe_i32
27 ; SI: v_bfe_i32
36 ; SI: v_bfe_i32
45 ; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 2, 8
54 ; SI-NOT: {{[^@]}}bfe
55 ; SI: s_endpgm
64 ; SI-NOT: {{[^@]}}bfe
[all …]
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| D | load-i1.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-pr…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check…
6 ; SI: buffer_load_ubyte
7 ; SI: v_and_b32_e32 v{{[0-9]+}}, 1
8 ; SI: buffer_store_byte
9 ; SI: s_endpgm
20 ; SI: ds_read_u8
21 ; SI: v_and_b32_e32 v{{[0-9]+}}, 1
22 ; SI: ds_write_b8
23 ; SI: s_endpgm
[all …]
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| D | valu-i1.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-misched -asm-verbose < %s | FileChe…
5 ; SI-LABEL: @test_if
8 ; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
9 ; SI: v_mov_b32_e32 v{{[0-9]}}, -1
44 ; SI-LABEL: @simple_test_v_if
45 ; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}}
46 ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc
47 ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]]
49 ; SI: ; BB#1
50 ; SI: buffer_store_dword
[all …]
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| D | llvm.AMDGPU.bfe.u32.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-pr…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check…
8 ; SI: v_bfe_u32
17 ; SI: v_bfe_u32
26 ; SI: v_bfe_u32
35 ; SI: v_bfe_u32
44 ; SI-NOT: {{[^@]}}bfe
45 ; SI: s_endpgm
54 ; SI-NOT: {{[^@]}}bfe
55 ; SI: s_endpgm
[all …]
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| D | fminnum.f64.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
11 ; SI: v_min_f64
19 ; SI: v_min_f64
20 ; SI: v_min_f64
28 ; SI: v_min_f64
29 ; SI: v_min_f64
30 ; SI: v_min_f64
31 ; SI: v_min_f64
39 ; SI: v_min_f64
[all …]
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| D | fmaxnum.f64.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
11 ; SI: v_max_f64
19 ; SI: v_max_f64
20 ; SI: v_max_f64
28 ; SI: v_max_f64
29 ; SI: v_max_f64
30 ; SI: v_max_f64
31 ; SI: v_max_f64
39 ; SI: v_max_f64
[all …]
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| D | insert_vector_elt.ll | 1 ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
12 ; SI-LABEL: {{^}}insertelement_v4f32_0:
24 ; SI-LABEL: {{^}}insertelement_v4f32_1:
31 ; SI-LABEL: {{^}}insertelement_v4f32_2:
38 ; SI-LABEL: {{^}}insertelement_v4f32_3:
45 ; SI-LABEL: {{^}}insertelement_v4i32_0:
52 ; SI-LABEL: {{^}}dynamic_insertelement_v2f32:
53 ; SI: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000
54 ; SI: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]]
[all …]
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| D | llvm.AMDGPU.div_scale.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
8 ; SI-LABEL @test_div_scale_f32_1:
9 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
10 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
11 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
12 ; SI: buffer_store_dword [[RESULT0]]
13 ; SI: s_endpgm
28 ; SI-LABEL @test_div_scale_f32_2:
29 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
30 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64…
[all …]
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| D | reorder-stores.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s
4 ; SI-LABEL: {{^}}no_reorder_v2f64_global_load_store:
5 ; SI: buffer_load_dwordx4
6 ; SI: buffer_load_dwordx4
7 ; SI: buffer_store_dwordx4
8 ; SI: buffer_store_dwordx4
9 ; SI: s_endpgm
18 ; SI-LABEL: {{^}}no_reorder_scalarized_v2f64_local_load_store:
19 ; SI: ds_read_b64
[all …]
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| D | mad-combine.ll | 3 … -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-…
4 …ify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-…
5 …achineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-STD -check-…
8 …contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM -che…
9 …contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM-SLOW…
18 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
19 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
20 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64…
22 ; SI-STD: v_mac_f32_e32 [[C]], [[B]], [[A]]
24 ; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
[all …]
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| D | uint_to_fp.f64.ll | 1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
5 ; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64
6 ; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
7 ; SI-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
8 ; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
9 ; SI-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
10 ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
11 ; SI: buffer_store_dwordx2 [[RESULT]]
21 ; SI-LABEL: {{^}}s_uint_to_fp_i64_to_f64
28 ; SI-LABEL: {{^}}s_uint_to_fp_v2i64_to_v2f64
[all …]
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| /external/llvm/lib/Object/ |
| D | Object.cpp | 31 inline section_iterator *unwrap(LLVMSectionIteratorRef SI) { in unwrap() argument
32 return reinterpret_cast<section_iterator*>(SI); in unwrap()
36 wrap(const section_iterator *SI) { in wrap() argument
38 (const_cast<section_iterator*>(SI)); in wrap()
41 inline symbol_iterator *unwrap(LLVMSymbolIteratorRef SI) { in unwrap() argument
42 return reinterpret_cast<symbol_iterator*>(SI); in unwrap()
46 wrap(const symbol_iterator *SI) { in wrap() argument
48 (const_cast<symbol_iterator*>(SI)); in wrap()
51 inline relocation_iterator *unwrap(LLVMRelocationIteratorRef SI) { in unwrap() argument
52 return reinterpret_cast<relocation_iterator*>(SI); in unwrap()
[all …]
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| /external/boringssl/src/ssl/test/runner/curve25519/ |
| D | square_amd64.s | 13 MOVQ in+8(FP), SI
28 MOVQ 0(SI),AX
29 MULQ 0(SI)
32 MOVQ 0(SI),AX
34 MULQ 8(SI)
37 MOVQ 0(SI),AX
39 MULQ 16(SI)
42 MOVQ 0(SI),AX
44 MULQ 24(SI)
47 MOVQ 0(SI),AX
[all …]
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