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Searched refs:SPR (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/Target/ARM/
DARMInstrVFP.td93 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
95 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]> {
107 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
109 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]> {
290 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
292 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> {
306 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
308 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
322 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
324 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>;
[all …]
DARMRegisterInfo.td272 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
273 let AltOrders = [(add (decimate SPR, 2), SPR),
274 (add (decimate SPR, 4),
275 (decimate SPR, 2),
276 (decimate (rotl SPR, 1), 4),
277 (decimate (rotl SPR, 1), 2))];
283 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
303 // 32-bit SPR subregs).
320 // Subset of QPR that have 32-bit SPR subregs.
DARMInstrNEON.td4219 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4221 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4223 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4225 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
5932 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5934 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5935 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5937 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5944 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5945 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.td42 // SPR - One of the 32-bit special-purpose registers
43 class SPR<bits<10> num, string n> : PPCReg<n> {
205 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
207 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
210 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
211 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
214 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
217 // (which really is SPR register 1); this is the only bit interesting to a
219 def CARRY: SPR<1, "ca">, DwarfRegNum<[76]>;
DPPCInstrFormats.td1140 bits<10> SPR;
1143 let Inst{11} = SPR{4};
1144 let Inst{12} = SPR{3};
1145 let Inst{13} = SPR{2};
1146 let Inst{14} = SPR{1};
1147 let Inst{15} = SPR{0};
1148 let Inst{16} = SPR{9};
1149 let Inst{17} = SPR{8};
1150 let Inst{18} = SPR{7};
1151 let Inst{19} = SPR{6};
[all …]
DPPCInstr64Bit.td333 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RT), (ins i32imm:$SPR),
334 "mfspr $RT, $SPR", IIC_SprMFSPR>;
335 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RT),
336 "mtspr $SPR, $RT", IIC_SprMTSPR>;
340 // 64-bit SPR manipulation instrs.
DPPCInstrInfo.td2226 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RT), (ins i32imm:$SPR),
2227 "mfspr $RT, $SPR", IIC_SprMFSPR>;
2228 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT),
2229 "mtspr $SPR, $RT", IIC_SprMTSPR>;
2231 def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR),
2232 "mftb $RT, $SPR", IIC_SprMFTB>;
2269 // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
3589 def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR),
3590 "mfdcr $RT, $SPR", IIC_SprMFSPR>, Requires<[IsPPC4xx]>;
3591 def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR),
[all …]
/external/llvm/lib/Transforms/InstCombine/
DInstCombineSelect.cpp1070 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local
1071 auto SPF = SPR.Flavor; in visitSelectInst()
1077 CmpInst::Predicate Pred = getCmpPredicateForMinMax(SPF, SPR.Ordered); in visitSelectInst()
/external/valgrind/docs/internals/
D3_3_BUGSTATUS.txt33 dis_proc_ctl(ppc)(mfspr,SPR)(0x11F)
/external/llvm/test/CodeGen/ARM/
Dvdup.ll336 ; Check that an SPR splat produces a vdup.
/external/valgrind/VEX/priv/
Dguest_ppc_toIR.c7152 UInt SPR = b11to20; in dis_proc_ctl() local
7166 SPR = ((SPR & 0x1F) << 5) | ((SPR >> 5) & 0x1F); in dis_proc_ctl()
7221 switch (SPR) { // Choose a register... in dis_proc_ctl()
7278 UInt arg = SPR==268 ? 0 : 1; in dis_proc_ctl()
7293 DIP("mfspr r%u,%u", rD_addr, SPR); in dis_proc_ctl()
7314 DIP("mfspr r%u,%u", rD_addr, SPR); in dis_proc_ctl()
7319 vex_printf("dis_proc_ctl(ppc)(mfspr,SPR)(0x%x)\n", SPR); in dis_proc_ctl()
7390 switch (SPR) { // Choose a register... in dis_proc_ctl()
7432 vex_printf("dis_proc_ctl(ppc)(mtspr,SPR)(%u)\n", SPR); in dis_proc_ctl()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGBuilder.cpp2470 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS); in visitSelect() local
2472 switch (SPR.Flavor) { in visitSelect()
2478 switch (SPR.NaNBehavior) { in visitSelect()
2495 switch (SPR.NaNBehavior) { in visitSelect()
/external/bison/po/
Dsv.po190 " -L, --language=SPRÅK ange programspråk för utmatning\n"
/external/webrtc/talk/media/testdata/
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/external/jetty/
DVERSION.txt2948 + SPR-3682 - dont hide forward attr in include.