Searched refs:ShiftImm (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 171 uint64_t ShiftImm, bool SetFlags = false,
176 uint64_t ShiftImm, bool SetFlags = false,
202 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
210 uint64_t ShiftImm);
1285 unsigned ShiftImm; in emitAddSub_ri() local
1287 ShiftImm = 0; in emitAddSub_ri()
1289 ShiftImm = 12; in emitAddSub_ri()
1318 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1326 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument
1334 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 496 unsigned ShiftImm; // shift for OffsetReg. member
506 unsigned ShiftImm; member
518 unsigned ShiftImm; member
524 unsigned ShiftImm; member
1194 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1211 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1732 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); in addRegShiftedRegOperands()
1741 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); in addRegShiftedImmOperands()
2054 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
2233 Memory.ShiftImm, Memory.ShiftType); in addMemRegOffsetOperands()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 2765 unsigned ShiftImm; in SelectShift() local
2768 ShiftImm = CI->getZExtValue(); in SelectShift()
2772 if (ShiftImm == 0 || ShiftImm >=32) in SelectShift()
2796 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1165 int64_t ShiftImm = 32 - (Size * 8); in emitSignExtendToI32InReg() local
1167 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
1168 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); in emitSignExtendToI32InReg()
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