/external/mesa3d/src/mesa/program/ |
D | prog_opt_constant_fold.c | 39 if (inst->SrcReg[i].File != PROGRAM_CONSTANT) in src_regs_are_constant() 146 get_value(prog, &inst->SrcReg[0], a); in _mesa_constant_fold() 147 get_value(prog, &inst->SrcReg[1], b); in _mesa_constant_fold() 155 inst->SrcReg[0] = src_reg_for_vec4(prog, result); in _mesa_constant_fold() 157 inst->SrcReg[1].File = PROGRAM_UNDEFINED; in _mesa_constant_fold() 158 inst->SrcReg[1].Swizzle = SWIZZLE_NOOP; in _mesa_constant_fold() 175 get_value(prog, &inst->SrcReg[0], a); in _mesa_constant_fold() 176 get_value(prog, &inst->SrcReg[1], b); in _mesa_constant_fold() 177 get_value(prog, &inst->SrcReg[2], c); in _mesa_constant_fold() 185 inst->SrcReg[0] = src_reg_for_vec4(prog, result); in _mesa_constant_fold() [all …]
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D | programopt.c | 94 newInst[i].SrcReg[0].File = PROGRAM_STATE_VAR; in _mesa_insert_mvp_dp4_code() 95 newInst[i].SrcReg[0].Index = mvpRef[i]; in _mesa_insert_mvp_dp4_code() 96 newInst[i].SrcReg[0].Swizzle = SWIZZLE_NOOP; in _mesa_insert_mvp_dp4_code() 97 newInst[i].SrcReg[1].File = PROGRAM_INPUT; in _mesa_insert_mvp_dp4_code() 98 newInst[i].SrcReg[1].Index = VERT_ATTRIB_POS; in _mesa_insert_mvp_dp4_code() 99 newInst[i].SrcReg[1].Swizzle = SWIZZLE_NOOP; in _mesa_insert_mvp_dp4_code() 166 newInst[0].SrcReg[0].File = PROGRAM_INPUT; in _mesa_insert_mvp_mad_code() 167 newInst[0].SrcReg[0].Index = VERT_ATTRIB_POS; in _mesa_insert_mvp_mad_code() 168 newInst[0].SrcReg[0].Swizzle = SWIZZLE_XXXX; in _mesa_insert_mvp_mad_code() 169 newInst[0].SrcReg[1].File = PROGRAM_STATE_VAR; in _mesa_insert_mvp_mad_code() [all …]
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D | prog_parameter_layout.c | 131 if (inst->SrcReg[i].Base.RelAddr) { in _mesa_layout_parameters() 134 if (!inst->SrcReg[i].Symbol->pass1_done) { in _mesa_layout_parameters() 137 inst->SrcReg[i].Symbol->param_binding_begin, in _mesa_layout_parameters() 138 inst->SrcReg[i].Symbol->param_binding_length); in _mesa_layout_parameters() 145 inst->SrcReg[i].Symbol->param_binding_begin = new_begin; in _mesa_layout_parameters() 146 inst->SrcReg[i].Symbol->pass1_done = 1; in _mesa_layout_parameters() 153 inst->Base.SrcReg[i] = inst->SrcReg[i].Base; in _mesa_layout_parameters() 154 inst->Base.SrcReg[i].Index += in _mesa_layout_parameters() 155 inst->SrcReg[i].Symbol->param_binding_begin; in _mesa_layout_parameters() 166 const int idx = inst->SrcReg[i].Base.Index; in _mesa_layout_parameters() [all …]
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D | prog_execute.c | 398 inst->SrcReg[0].File == PROGRAM_INPUT && in fetch_texel() 399 inst->SrcReg[0].Index == FRAG_ATTRIB_TEX0 + inst->TexSrcUnit) { in fetch_texel() 401 GLuint attr = inst->SrcReg[0].Index; in fetch_texel() 669 fetch_vector4(&inst->SrcReg[0], machine, a); in _mesa_execute_program() 680 fetch_vector4(&inst->SrcReg[0], machine, a); in _mesa_execute_program() 681 fetch_vector4(&inst->SrcReg[1], machine, b); in _mesa_execute_program() 697 fetch_vector4ui(&inst->SrcReg[0], machine, a); in _mesa_execute_program() 698 fetch_vector4ui(&inst->SrcReg[1], machine, b); in _mesa_execute_program() 709 fetch_vector4(&inst->SrcReg[0], machine, t); in _mesa_execute_program() 770 fetch_vector4(&inst->SrcReg[0], machine, a); in _mesa_execute_program() [all …]
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D | prog_optimize.c | 117 const GLuint coord = GET_SWZ(inst->SrcReg[arg].Swizzle, comp); in get_src_arg_mask() 144 src_comp = GET_SWZ(mov->SrcReg[0].Swizzle, comp); in get_dst_mask_for_mov() 228 if (inst->SrcReg[j].File == file) { in replace_regs() 229 GLuint index = inst->SrcReg[j].Index; in replace_regs() 231 inst->SrcReg[j].Index = map[index]; in replace_regs() 274 if (inst->SrcReg[j].File == PROGRAM_TEMPORARY) { in _mesa_remove_dead_code_global() 275 const GLuint index = inst->SrcReg[j].Index; in _mesa_remove_dead_code_global() 280 if (inst->SrcReg[j].RelAddr) { in _mesa_remove_dead_code_global() 287 const GLuint swz = GET_SWZ(inst->SrcReg[j].Swizzle, comp); in _mesa_remove_dead_code_global() 412 if (inst->SrcReg[j].RelAddr || in find_next_use() [all …]
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D | nvvertparse.c | 815 if (!Parse_SwizzleSrcReg(parseState, &inst->SrcReg[0])) in Parse_UnaryOpInstruction() 847 if (!Parse_SwizzleSrcReg(parseState, &inst->SrcReg[0])) in Parse_BiOpInstruction() 855 if (!Parse_SwizzleSrcReg(parseState, &inst->SrcReg[1])) in Parse_BiOpInstruction() 863 if (inst->SrcReg[0].File == PROGRAM_ENV_PARAM && in Parse_BiOpInstruction() 864 inst->SrcReg[1].File == PROGRAM_ENV_PARAM && in Parse_BiOpInstruction() 865 inst->SrcReg[0].Index != inst->SrcReg[1].Index) in Parse_BiOpInstruction() 869 if (inst->SrcReg[0].File == PROGRAM_INPUT && in Parse_BiOpInstruction() 870 inst->SrcReg[1].File == PROGRAM_INPUT && in Parse_BiOpInstruction() 871 inst->SrcReg[0].Index != inst->SrcReg[1].Index) in Parse_BiOpInstruction() 894 if (!Parse_SwizzleSrcReg(parseState, &inst->SrcReg[0])) in Parse_TriOpInstruction() [all …]
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
D | radeon_program_tex.c | 70 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in scale_texcoords() 71 inst_mov->U.I.SrcReg[1].File = RC_FILE_CONSTANT; in scale_texcoords() 72 inst_mov->U.I.SrcReg[1].Index = in scale_texcoords() 76 reset_srcreg(&inst->U.I.SrcReg[0]); in scale_texcoords() 77 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; in scale_texcoords() 78 inst->U.I.SrcReg[0].Index = temp; in scale_texcoords() 93 inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide() 96 inst_rcp->U.I.SrcReg[0].Swizzle = in projective_divide() 97 RC_MAKE_SWIZZLE_SMEAR(GET_SWZ(inst->U.I.SrcReg[0].Swizzle, 3)); in projective_divide() 103 inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in projective_divide() [all …]
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D | radeon_optimize.c | 76 &reader_data->Writer->U.I.PreSub.SrcReg[0], in copy_propagate_scan_read() 77 &reader_data->Writer->U.I.PreSub.SrcReg[1])) { in copy_propagate_scan_read() 91 if(reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_TEMPORARY && in copy_propagate_scan_read() 92 reader_data->Writer->U.I.SrcReg[0].File != RC_FILE_INPUT && in copy_propagate_scan_read() 162 …_data.Readers[i].U.I.Src = chain_srcregs(*reader_data.Readers[i].U.I.Src, inst_mov->U.I.SrcReg[0]); in copy_propagate() 164 if (inst_mov->U.I.SrcReg[0].File == RC_FILE_PRESUB) in copy_propagate() 215 if (is_src_uniform_constant(inst->U.I.SrcReg[2], &swz, &negate)) { in constant_folding_mad() 222 if (is_src_uniform_constant(inst->U.I.SrcReg[1], &swz, &negate)) { in constant_folding_mad() 226 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW; in constant_folding_mad() 227 inst->U.I.SrcReg[1] = inst->U.I.SrcReg[2]; in constant_folding_mad() [all …]
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D | r3xx_vertprog.c | 43 (PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[x]), \ 48 t_src_class(vpi->SrcReg[x].File), \ 49 RC_MASK_NONE) | (vpi->SrcReg[x].RelAddr << 4)) 197 inst[1] = t_src(vp, &vpi->SrcReg[0]); in ei_vector1() 213 inst[1] = t_src(vp, &vpi->SrcReg[0]); in ei_vector2() 214 inst[2] = t_src(vp, &vpi->SrcReg[1]); in ei_vector2() 229 inst[1] = t_src_scalar(vp, &vpi->SrcReg[0]); in ei_math1() 247 …inst[1] = PVS_SRC_OPERAND(t_src_index(vp, &vpi->SrcReg[0]), t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizz… in ei_lit() 248 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 3)), // W in ei_lit() 250 t_swizzle(GET_SWZ(vpi->SrcReg[0].Swizzle, 1)), // Y in ei_lit() [all …]
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D | radeon_pair_translate.c | 44 inst->SrcReg[2] = inst->SrcReg[1]; in final_rewrite() 45 inst->SrcReg[1].File = RC_FILE_NONE; in final_rewrite() 46 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111; in final_rewrite() 47 inst->SrcReg[1].Negate = RC_MASK_NONE; in final_rewrite() 51 tmp = inst->SrcReg[2]; in final_rewrite() 52 inst->SrcReg[2] = inst->SrcReg[0]; in final_rewrite() 53 inst->SrcReg[0] = tmp; in final_rewrite() 66 inst->SrcReg[1].File = RC_FILE_NONE; in final_rewrite() 67 inst->SrcReg[1].Swizzle = RC_SWIZZLE_1111; in final_rewrite() 68 inst->SrcReg[2].File = RC_FILE_NONE; in final_rewrite() [all …]
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D | radeon_compiler.c | 123 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT) in rc_calculate_inputs_outputs() 124 c->Program.InputsRead |= 1 << inst->U.I.SrcReg[i].Index; in rc_calculate_inputs_outputs() 149 if (inst->U.I.SrcReg[i].File == RC_FILE_INPUT && inst->U.I.SrcReg[i].Index == input) { in rc_move_input() 150 inst->U.I.SrcReg[i].File = new_input.File; in rc_move_input() 151 inst->U.I.SrcReg[i].Index = new_input.Index; in rc_move_input() 152 inst->U.I.SrcReg[i].Swizzle = combine_swizzles(new_input.Swizzle, inst->U.I.SrcReg[i].Swizzle); in rc_move_input() 153 if (!inst->U.I.SrcReg[i].Abs) { in rc_move_input() 154 inst->U.I.SrcReg[i].Negate ^= new_input.Negate; in rc_move_input() 155 inst->U.I.SrcReg[i].Abs = new_input.Abs; in rc_move_input() 215 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; in rc_copy_output() [all …]
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D | radeon_dataflow_swizzles.c | 43 if (GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan) != RC_SWIZZLE_UNUSED) in rewrite_source() 47 c->SwizzleCaps->Split(inst->U.I.SrcReg[src], usemask, &split); in rewrite_source() 58 mov->U.I.SrcReg[0] = inst->U.I.SrcReg[src]; in rewrite_source() 64 SET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan, RC_SWIZZLE_UNUSED); in rewrite_source() 66 phase_refmask |= 1 << GET_SWZ(mov->U.I.SrcReg[0].Swizzle, chan); in rewrite_source() 71 masked_negate = split.Phase[phase] & mov->U.I.SrcReg[0].Negate; in rewrite_source() 73 mov->U.I.SrcReg[0].Negate = 0; in rewrite_source() 75 mov->U.I.SrcReg[0].Negate = RC_MASK_XYZW; in rewrite_source() 79 inst->U.I.SrcReg[src].File = RC_FILE_TEMPORARY; in rewrite_source() 80 inst->U.I.SrcReg[src].Index = tempreg; in rewrite_source() [all …]
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D | radeon_program_alu.c | 45 struct rc_dst_register DstReg, struct rc_src_register SrcReg) in emit1() argument 55 fpi->U.I.SrcReg[0] = SrcReg; in emit1() 73 fpi->U.I.SrcReg[0] = SrcReg0; in emit2() 74 fpi->U.I.SrcReg[1] = SrcReg1; in emit2() 93 fpi->U.I.SrcReg[0] = SrcReg0; in emit3() 94 fpi->U.I.SrcReg[1] = SrcReg1; in emit3() 95 fpi->U.I.SrcReg[2] = SrcReg2; in emit3() 208 if (inst->U.I.SrcReg[i].File == RC_FILE_TEMPORARY && in is_dst_safe_to_reuse() 209 inst->U.I.SrcReg[i].Index == inst->U.I.DstReg.Index) in is_dst_safe_to_reuse() 232 struct rc_src_register src = inst->U.I.SrcReg[0]; in transform_ABS() [all …]
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D | radeon_vert_fc.c | 107 new_inst->U.I.SrcReg[0].Index = 0; in lower_bgnloop() 108 new_inst->U.I.SrcReg[0].File = RC_FILE_NONE; in lower_bgnloop() 109 new_inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000; in lower_bgnloop() 117 build_pred_src(&new_inst->U.I.SrcReg[0], fc_state); in lower_bgnloop() 127 new_inst->U.I.SrcReg[1].Index = 0; in lower_bgnloop() 128 new_inst->U.I.SrcReg[1].File = RC_FILE_NONE; in lower_bgnloop() 129 new_inst->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_0000; in lower_bgnloop() 141 inst->U.I.SrcReg[0].Index = 0; in lower_brk() 142 inst->U.I.SrcReg[0].File = RC_FILE_NONE; in lower_brk() 143 inst->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_0000; in lower_brk() [all …]
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D | radeon_emulate_loops.c | 99 if(!rc_src_reg_is_immediate(value->C, inst->U.I.SrcReg[0].File, in update_const_value() 100 inst->U.I.SrcReg[0].Index)){ in update_const_value() 106 inst->U.I.SrcReg[0].Index, in update_const_value() 107 inst->U.I.SrcReg[0].Swizzle, in update_const_value() 108 inst->U.I.SrcReg[0].Negate, 0); in update_const_value() 140 if(inst->U.I.SrcReg[0].File == RC_FILE_TEMPORARY && in get_incr_amount() 141 inst->U.I.SrcReg[0].Index == count_inst->Index && in get_incr_amount() 142 inst->U.I.SrcReg[0].Swizzle == count_inst->Swz){ in get_incr_amount() 144 } else if( inst->U.I.SrcReg[1].File == RC_FILE_TEMPORARY && in get_incr_amount() 145 inst->U.I.SrcReg[1].Index == count_inst->Index && in get_incr_amount() [all …]
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D | radeon_emulate_branches.c | 79 inst_mov->U.I.SrcReg[0] = inst->U.I.SrcReg[0]; in handle_if() 81 inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; in handle_if() 82 inst->U.I.SrcReg[0].Index = inst_mov->U.I.DstReg.Index; in handle_if() 83 inst->U.I.SrcReg[0].Swizzle = 0; in handle_if() 84 inst->U.I.SrcReg[0].Abs = 0; in handle_if() 85 inst->U.I.SrcReg[0].Negate = 0; in handle_if() 169 inst_mov->U.I.SrcReg[0].File = RC_FILE_TEMPORARY; in allocate_and_insert_proxies() 170 inst_mov->U.I.SrcReg[0].Index = index; in allocate_and_insert_proxies() 188 inst_cmp->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0]; in inject_cmp() 189 inst_cmp->U.I.SrcReg[0].Abs = 1; in inject_cmp() [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCRegisterInfo.h | 26 inline static unsigned getCRFromCRBit(unsigned SrcReg) { in getCRFromCRBit() argument 28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit() 29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit() 31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit() 32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit() 34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit() 35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit() 37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || in getCRFromCRBit() 38 SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN) in getCRFromCRBit() 40 else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT || in getCRFromCRBit() [all …]
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/external/mesa3d/src/mesa/state_tracker/ |
D | st_mesa_to_tgsi.c | 340 const struct prog_src_register *SrcReg ) in translate_src() argument 342 struct ureg_src src = src_register( t, SrcReg->File, SrcReg->Index ); in translate_src() 344 if (t->procType == TGSI_PROCESSOR_GEOMETRY && SrcReg->HasIndex2) { in translate_src() 345 src = src_register( t, SrcReg->File, SrcReg->Index2 ); in translate_src() 346 if (SrcReg->RelAddr2) in translate_src() 348 SrcReg->Index); in translate_src() 350 src = ureg_src_dimension( src, SrcReg->Index); in translate_src() 354 GET_SWZ( SrcReg->Swizzle, 0 ) & 0x3, in translate_src() 355 GET_SWZ( SrcReg->Swizzle, 1 ) & 0x3, in translate_src() 356 GET_SWZ( SrcReg->Swizzle, 2 ) & 0x3, in translate_src() [all …]
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D | st_atom_pixeltransfer.c | 165 inst[ic].SrcReg[0].File = PROGRAM_INPUT; in get_pixel_transfer_program() 166 inst[ic].SrcReg[0].Index = FRAG_ATTRIB_TEX0; in get_pixel_transfer_program() 189 inst[ic].SrcReg[0].File = PROGRAM_TEMPORARY; in get_pixel_transfer_program() 190 inst[ic].SrcReg[0].Index = colorTemp; in get_pixel_transfer_program() 191 inst[ic].SrcReg[1].File = PROGRAM_STATE_VAR; in get_pixel_transfer_program() 192 inst[ic].SrcReg[1].Index = scale_p; in get_pixel_transfer_program() 193 inst[ic].SrcReg[2].File = PROGRAM_STATE_VAR; in get_pixel_transfer_program() 194 inst[ic].SrcReg[2].Index = bias_p; in get_pixel_transfer_program() 219 inst[ic].SrcReg[0].File = PROGRAM_TEMPORARY; in get_pixel_transfer_program() 220 inst[ic].SrcReg[0].Index = colorTemp; in get_pixel_transfer_program() [all …]
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/external/llvm/lib/Target/ARM/ |
D | Thumb1InstrInfo.cpp | 42 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument 48 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg() 51 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) in copyPhysReg() 54 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg() 64 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 72 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument 76 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && in storeRegToStackSlot() 77 isARMLowRegister(SrcReg))) && "Unknown regclass!"); in storeRegToStackSlot() 80 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && in storeRegToStackSlot() 81 isARMLowRegister(SrcReg))) { in storeRegToStackSlot() [all …]
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/external/mesa3d/src/mesa/drivers/dri/i915/ |
D | i915_fragprog.c | 275 GLuint coord = src_vector( p, &inst->SrcReg[0], program); \ 292 (N<1)?0:src_vector( p, &inst->SrcReg[0], program), \ 293 (N<2)?0:src_vector( p, &inst->SrcReg[1], program), \ 294 (N<3)?0:src_vector( p, &inst->SrcReg[2], program)); \ 328 if (inst->SrcReg[a].File == PROGRAM_TEMPORARY) { in calc_live_regs() 331 if (inst->SrcReg[a].Index >= I915_MAX_TEMPORARY) in calc_live_regs() 334 regsUsed |= 1 << inst->SrcReg[a].Index; in calc_live_regs() 337 const unsigned field = GET_SWZ(inst->SrcReg[a].Swizzle, c); in calc_live_regs() 340 live_components[inst->SrcReg[a].Index] |= (1U << field); in calc_live_regs() 414 src0 = src_vector(p, &inst->SrcReg[0], program); in upload_program() [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonPeephole.cpp | 142 unsigned SrcReg = Src.getReg(); in runOnMachineFunction() local 145 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction() 149 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction() 164 unsigned SrcReg = Src2.getReg(); in runOnMachineFunction() local 165 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction() 181 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction() local 183 std::make_pair(*&SrcReg, Hexagon::subreg_hireg); in runOnMachineFunction() 193 unsigned SrcReg = Src.getReg(); in runOnMachineFunction() local 196 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction() 200 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction() [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.cpp | 81 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument 87 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg() 92 } else if (Mips::CCRRegClass.contains(SrcReg)) in copyPhysReg() 94 else if (Mips::FGR32RegClass.contains(SrcReg)) in copyPhysReg() 96 else if (Mips::HI32RegClass.contains(SrcReg)) { in copyPhysReg() 98 SrcReg = 0; in copyPhysReg() 99 } else if (Mips::LO32RegClass.contains(SrcReg)) { in copyPhysReg() 101 SrcReg = 0; in copyPhysReg() 102 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) in copyPhysReg() 104 else if (Mips::LO32DSPRegClass.contains(SrcReg)) in copyPhysReg() [all …]
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/external/mesa3d/src/mesa/drivers/dri/r200/ |
D | r200_fragshader.c | 170 inst->SrcReg[optype][0], 1, &tfactor); in r200UpdateFSArith() 172 inst->SrcReg[optype][1], 2, &tfactor); in r200UpdateFSArith() 180 inst->SrcReg[optype][0], 2, &tfactor); in r200UpdateFSArith() 185 inst->SrcReg[optype][2], 2, &tfactor); in r200UpdateFSArith() 189 inst->SrcReg[optype][0], 0, &tfactor); in r200UpdateFSArith() 191 inst->SrcReg[optype][1], 1, &tfactor); in r200UpdateFSArith() 197 inst->SrcReg[optype][0], 2, &tfactor); in r200UpdateFSArith() 199 inst->SrcReg[optype][1], 1, &tfactor); in r200UpdateFSArith() 201 inst->SrcReg[optype][2], 0, &tfactor); in r200UpdateFSArith() 206 inst->SrcReg[optype][0], 0, &tfactor); in r200UpdateFSArith() [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.cpp | 439 unsigned SrcReg = Cond[2].getReg(); in insertSelect() local 442 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect() 444 .addReg(SrcReg) in insertSelect() 448 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect() 450 .addReg(SrcReg) in insertSelect() 595 unsigned &SrcReg, unsigned &DstReg, in isCoalescableExtInstr() argument 607 SrcReg = MI.getOperand(1).getReg(); in isCoalescableExtInstr() 651 bool AArch64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, in analyzeCompare() argument 670 SrcReg = MI->getOperand(1).getReg(); in analyzeCompare() 679 SrcReg = MI->getOperand(1).getReg(); in analyzeCompare() [all …]
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