| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 187 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding() argument
197 if ((FirstUseIdx + UseIdx) >= LastUseIdx) in hasPipelineForwarding()
201 Forwardings[FirstUseIdx + UseIdx]; in hasPipelineForwarding()
208 unsigned UseClass, unsigned UseIdx) const { in getOperandLatency() argument
216 int UseCycle = getOperandCycle(UseClass, UseIdx); in getOperandLatency()
222 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| D | MCSubtargetInfo.h | 135 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles() argument
142 if (I->UseIdx < UseIdx) in getReadAdvanceCycles()
144 if (I->UseIdx > UseIdx) in getReadAdvanceCycles()
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| D | MCSchedule.h | 87 unsigned UseIdx; member
92 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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| /external/llvm/lib/CodeGen/ |
| D | LiveRangeEdit.cpp | 84 SlotIndex UseIdx) const { in allUsesAvailableAt()
86 UseIdx = UseIdx.getRegSlot(true); in allUsesAvailableAt()
107 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) in allUsesAvailableAt()
110 if (OVNI != li.getVNInfoAt(UseIdx)) in allUsesAvailableAt()
117 SlotIndex UseIdx, in canRematerializeAt() argument
140 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
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| D | TargetSchedule.cpp | 144 unsigned UseIdx = 0; in findUseIdx() local
148 ++UseIdx; in findUseIdx()
150 return UseIdx; in findUseIdx()
202 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency() local
203 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
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| D | LiveRangeCalc.cpp | 170 SlotIndex UseIdx; in extendToUses() local
175 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB()); in extendToUses()
187 UseIdx = Indexes->getInstructionIndex(MI).getRegSlot(isEarlyClobber); in extendToUses()
192 extend(LR, UseIdx, Reg); in extendToUses()
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| D | InlineSpiller.cpp | 867 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); in reMaterializeFor() local
868 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
877 DEBUG(dbgs() << UseIdx << '\t' << *MI); in reMaterializeFor()
889 if (!Edit->canRematerializeAt(RM, UseIdx, false)) { in reMaterializeFor()
891 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI); in reMaterializeFor()
899 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI); in reMaterializeFor()
930 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI << '\n'); in reMaterializeFor()
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| D | TargetInstrInfo.cpp | 984 SDNode *UseNode, unsigned UseIdx) const { in getOperandLatency()
995 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1074 const MachineInstr *UseMI, unsigned UseIdx) const { in getOperandLatency()
1077 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1111 const MachineInstr *UseMI, unsigned UseIdx) const { in computeOperandLatency()
1121 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); in computeOperandLatency()
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| D | RegisterCoalescer.cpp | 695 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); in removeCopyByCommutingDef() local
696 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
749 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); in removeCopyByCommutingDef() local
750 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); in removeCopyByCommutingDef()
770 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef()
1139 SlotIndex UseIdx = LIS->getInstructionIndex(&MI); in eliminateUndefCopy() local
1147 if (SR.liveAt(UseIdx)) { in eliminateUndefCopy()
1153 isLive = DstLI.liveAt(UseIdx); in eliminateUndefCopy()
1157 DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI); in eliminateUndefCopy()
1214 SlotIndex UseIdx = MIIdx.getRegSlot(true); in updateRegDefsUses() local
[all …]
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| D | SplitKit.h | 319 SlotIndex UseIdx,
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| D | MachineVerifier.cpp | 1052 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); in checkLiveness() local
1057 LiveQueryResult LRQ = LR->Query(UseIdx); in checkLiveness()
1060 errs() << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI) in checkLiveness()
1075 LiveQueryResult LRQ = LI.Query(UseIdx); in checkLiveness()
1078 errs() << UseIdx << " is not live in " << LI << '\n'; in checkLiveness()
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| D | TwoAddressInstructionPass.cpp | 1590 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber); in processTiedPairs() local
1591 if (I->end == UseIdx) in processTiedPairs()
1592 LI.removeSegment(LastCopyIdx, UseIdx); in processTiedPairs()
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| D | MachineInstr.cpp | 1291 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1293 MachineOperand &UseMO = getOperand(UseIdx); in tieOperands()
1310 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); in tieOperands()
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| D | SplitKit.cpp | 421 SlotIndex UseIdx, in defFromParent() argument
434 if (Edit->canRematerializeAt(RM, UseIdx, true)) { in defFromParent()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 287 unsigned UseIdx) const override;
290 SDNode *UseNode, unsigned UseIdx) const override;
319 unsigned UseIdx, unsigned UseAlign) const;
323 unsigned UseIdx, unsigned UseAlign) const;
328 unsigned UseIdx, unsigned UseAlign) const;
343 unsigned UseIdx) const override;
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| D | ARMBaseInstrInfo.cpp | 3230 unsigned UseIdx, unsigned UseAlign) const { in getVSTMUseCycle() argument
3231 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
3233 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
3270 unsigned UseIdx, unsigned UseAlign) const { in getSTMUseCycle() argument
3271 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
3273 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
3300 unsigned UseIdx, unsigned UseAlign) const { in getOperandLatency() argument
3304 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3305 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
3355 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 122 unsigned UseIdx) const override;
125 SDNode *UseNode, unsigned UseIdx) const override { in getOperandLatency() argument
127 UseNode, UseIdx); in getOperandLatency()
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| D | PPCVSXSwapRemoval.cpp | 672 int UseIdx = SwapMap[&UseMI]; in recordUnoptimizableWebs() local
674 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || in recordUnoptimizableWebs()
675 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
683 DEBUG(dbgs() << " use " << UseIdx << ": "); in recordUnoptimizableWebs()
736 int UseIdx = SwapMap[&UseMI]; in markSwapsForRemoval() local
737 SwapVector[UseIdx].WillRemove = 1; in markSwapsForRemoval()
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| D | PPCInstrInfo.cpp | 143 unsigned UseIdx) const { in getOperandLatency()
145 UseMI, UseIdx); in getOperandLatency()
1210 unsigned UseIdx; in FoldImmediate() local
1211 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx) in FoldImmediate()
1212 if (UseMI->getOperand(UseIdx).isReg() && in FoldImmediate()
1213 UseMI->getOperand(UseIdx).getReg() == Reg) in FoldImmediate()
1216 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI"); in FoldImmediate()
1217 assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); in FoldImmediate()
1219 const MCOperandInfo *UseInfo = &UseMCID.OpInfo[UseIdx]; in FoldImmediate()
1248 UseMI->getOperand(UseIdx).setReg(ZeroReg); in FoldImmediate()
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| /external/llvm/include/llvm/CodeGen/ |
| D | LiveRangeEdit.h | 89 SlotIndex UseIdx) const;
186 SlotIndex UseIdx,
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| D | MachineInstr.h | 998 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1154 SDNode *UseNode, unsigned UseIdx) const;
1167 unsigned UseIdx) const;
1173 const MachineInstr *UseMI, unsigned UseIdx)
1207 const MachineInstr *UseMI, unsigned UseIdx) const { in hasHighOperandLatency() argument
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| /external/llvm/utils/TableGen/ |
| D | SubtargetEmitter.cpp | 975 for (unsigned UseIdx = 0, EndIdx = Reads.size(); in GenSchedClassTables() local
976 UseIdx != EndIdx; ++UseIdx) { in GenSchedClassTables()
978 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1000 RAEntry.UseIdx = UseIdx; in GenSchedClassTables()
1112 OS << " {" << RAEntry.UseIdx << ", " in EmitSchedClassTables()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 486 unsigned UseIdx) const override;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 1006 unsigned UseIdx = GroupIdx.back() + 1; in EmitSpecialNode() local
1008 MIB->tieOperands(DefIdx + j, UseIdx + j); in EmitSpecialNode()
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