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Searched refs:brtarget (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td68 (BCOND brtarget:$imm, condVal)>;
72 (BCONDA brtarget:$imm, condVal)>;
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
DSparcInstrInfo.td110 def brtarget : Operand<OtherVT> {
662 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
708 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
711 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
748 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
751 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
/external/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td329 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
341 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
342 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
343 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
344 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
346 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
347 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
349 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
350 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
352 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
[all …]
DMips64InstrInfo.td208 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
209 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
210 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
211 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
212 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
213 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
308 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
370 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
372 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64,
377 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
[all …]
DMipsInstrInfo.td475 def brtarget : Operand<OtherVT> {
979 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
980 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
1041 PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
1042 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
1317 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1321 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1511 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1512 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1514 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
[all …]
DMipsInstrFPU.td512 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
514 def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
516 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
518 def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
557 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
559 def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
561 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
563 def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
DMips16InstrInfo.td41 FI16<op, (outs), (ins brtarget:$imm16),
99 FRI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
138 FEXT_I16<eop, (outs), (ins brtarget:$imm16),
201 FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
265 (ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
277 (ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
DMipsDSPInstrInfo.td518 dag InOperandList = (ins brtarget:$offset);
DMipsMSAInstrInfo.td1425 dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILInstrInfo.td73 def brtarget : Operand<OtherVT>;
184 (ins brtarget:$target, GPRI32:$src0),
188 (ins brtarget:$target, GPRF32:$src0),
221 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
DSIInstructions.td610 0x00000002, (ins brtarget:$target), "S_BRANCH",
616 0x00000004, (ins brtarget:$target, SCCReg:$scc),
620 0x00000005, (ins brtarget:$target, SCCReg:$scc),
627 0x00000006, (ins brtarget:$target, VCCReg:$vcc),
632 0x00000007, (ins brtarget:$target, VCCReg:$vcc),
639 0x00000008, (ins brtarget:$target, EXECReg:$exec),
644 0x00000009, (ins brtarget:$target, EXECReg:$exec),
980 (ins brtarget:$target, VCCReg:$vcc),
987 (ins brtarget:$target, VCCReg:$vcc),
DR600Instructions.td128 (ins brtarget:$target, R600_Pred:$p),
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td46 def brtarget : Operand<OtherVT>;
83 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
104 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
353 : InstBPF<(outs), (ins brtarget:$BrDst),
/external/llvm/lib/Target/AMDGPU/
DR600Instructions.td1299 (ins brtarget:$target, R600_Predicate_Bit:$p),
1306 (ins brtarget:$target),
1505 (ins brtarget:$target, rci:$src0),
1509 (ins brtarget:$target, rcf:$src0),
1534 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
DAMDGPUInstructions.td63 def brtarget : Operand<OtherVT>;
DSIInstructions.td1879 (ins SReg_64:$vcc, brtarget:$target),
1886 (ins SReg_64:$src, brtarget:$target),
1895 (ins SReg_64:$saved, brtarget:$target),
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td193 def brtarget : Operand<OtherVT>;
287 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
289 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
654 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
656 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td50 def A4_ext_b : T_Immext<brtarget>;
1566 (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset),
1641 (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
1699 (ins IntRegs:$src1, brtarget:$offset),
4006 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4052 : InstHexagon<(outs), (ins IntRegs:$Rs, IntRegs:$Rt, brtarget:$r9_2),
4106 : InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
4161 : InstHexagon<(outs), (ins IntRegs:$Rs, brtarget:$r9_2),
4215 (ins u6Imm:$U6, brtarget:$r9_2),
4235 (ins IntRegs:$Rs, brtarget:$r9_2),
DHexagonInstrInfo.td1441 : JInst<(outs), (ins brtarget:$dst),
1456 : JInst<(outs), (ins PredRegs:$src, brtarget:$dst),
1593 (J2_jump brtarget:$dst)>;
4607 def i : LOOP_iBase<mnemonic, brtarget>;
4608 def r : LOOP_rBase<mnemonic, brtarget>;
4626 def ENDLOOP0 : Endloop<(outs), (ins brtarget:$offset),
4633 def ENDLOOP1 : Endloop<(outs), (ins brtarget:$offset),
4643 : CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
4663 : CRInst <(outs), (ins brtarget:$r7_2, IntRegs:$Rs),
4690 : CRInst <(outs), (ins IntRegs:$Rs, brtarget:$r13_2),
DHexagonOperands.td580 def brtarget : Operand<OtherVT> {
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp3971 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; in DecodeThumb2BCCInstruction() local
3972 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; in DecodeThumb2BCCInstruction()
3973 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; in DecodeThumb2BCCInstruction()
3974 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; in DecodeThumb2BCCInstruction()
3975 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; in DecodeThumb2BCCInstruction()
3977 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) in DecodeThumb2BCCInstruction()
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td33 def brtarget : Operand<OtherVT>;
2648 def CBranch : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2652 def CBranchOther : NVPTXInst<(outs), (ins Int1Regs:$a, brtarget:$target),
2657 def GOTO : NVPTXInst<(outs), (ins brtarget:$target),
/external/llvm/docs/
DWritingAnLLVMBackend.rst973 For example, the X86 backend defines ``brtarget`` and ``brtarget8``, both
979 def brtarget : Operand<OtherVT>;
990 brtarget,
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td404 // FIXME: rename brtarget to t2_brtarget
405 def brtarget : Operand<OtherVT> {
4448 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4454 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td202 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),

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