Home
last modified time | relevance | path

Searched refs:fcvtas (Results 1 – 25 of 30) sorted by relevance

12

/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s91 fcvtas h12, h13
92 fcvtas s12, s13
93 fcvtas d21, d14
Darm64-fp-encoding.s254 fcvtas w1, d2
255 fcvtas x1, d2
256 fcvtas w1, s2
257 fcvtas x1, s2
258 fcvtas w1, h2
259 fcvtas x1, h2
261 ; CHECK: fcvtas w1, d2 ; encoding: [0x41,0x00,0x64,0x1e]
262 ; CHECK: fcvtas x1, d2 ; encoding: [0x41,0x00,0x64,0x9e]
263 ; CHECK: fcvtas w1, s2 ; encoding: [0x41,0x00,0x24,0x1e]
264 ; CHECK: fcvtas x1, s2 ; encoding: [0x41,0x00,0x24,0x9e]
[all …]
Dneon-simd-misc.s646 fcvtas v4.4h, v0.4h
647 fcvtas v6.8h, v8.8h
648 fcvtas v6.4s, v8.4s
649 fcvtas v6.2d, v8.2d
650 fcvtas v4.2s, v0.2s
Dfullfp16-neon-neg.s230 fcvtas h12, h13
362 fcvtas v4.4h, v0.4h
364 fcvtas v6.8h, v8.8h
Darm64-advsimd.s780 fcvtas.2s v0, v0
781 fcvtas.4s v0, v0
782 fcvtas.2d v0, v0
783 fcvtas s0, s0
784 fcvtas d0, d0 define
786 ; CHECK: fcvtas.2s v0, v0 ; encoding: [0x00,0xc8,0x21,0x0e]
787 ; CHECK: fcvtas.4s v0, v0 ; encoding: [0x00,0xc8,0x21,0x4e]
788 ; CHECK: fcvtas.2d v0, v0 ; encoding: [0x00,0xc8,0x61,0x4e]
789 ; CHECK: fcvtas s0, s0 ; encoding: [0x00,0xc8,0x21,0x5e]
790 ; CHECK: fcvtas d0, d0 ; encoding: [0x00,0xc8,0x61,0x5e]
Dneon-diagnostics.s5931 fcvtas v0.16b, v31.16b
5932 fcvtas v2.8h, v4.8h
5933 fcvtas v1.8b, v9.8b
5934 fcvtas v13.4h, v21.4h
7177 fcvtas s0, d0
7178 fcvtas d0, s0 define
Dbasic-a64-instructions.s2113 fcvtas w25, s26
2114 fcvtas x27, s28
2167 fcvtas w25, d26
2168 fcvtas x27, d28
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll8 ;CHECK: fcvtas w0, s0
10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)
16 ;CHECK: fcvtas x0, s0
18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)
24 ;CHECK: fcvtas w0, d0
26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)
32 ;CHECK: fcvtas x0, d0
34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)
38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone
39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone
[all …]
Dround-conv.ll244 ; CHECK: fcvtas w0, s0
254 ; CHECK: fcvtas x0, s0
264 ; CHECK: fcvtas w0, d0
274 ; CHECK: fcvtas x0, d0
Darm64-vcvt.ll6 ;CHECK: fcvtas.2s v0, v0
8 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A)
15 ;CHECK: fcvtas.4s v0, v0
17 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> %A)
24 ;CHECK: fcvtas.2d v0, v0
26 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A)
30 declare <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float>) nounwind readnone
31 declare <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float>) nounwind readnone
32 declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind readnone
/external/valgrind/docs/internals/
DMERGE_3_10_1.txt101 //340509 arm64: unhandled instruction fcvtas
127 //340632 arm64: unhandled instruction fcvtas
/external/vixl/doc/
Dchangelog.md93 `frinta`, `fcvtau` and `fcvtas`.
Dsupported-instructions.md1892 void fcvtas(const Register& rd, const VRegister& vn)
1899 void fcvtas(const VRegister& vd, const VRegister& vn)
/external/v8/test/cctest/
Dtest-disasm-arm64.cc1509 COMPARE(fcvtas(w0, s1), "fcvtas w0, s1"); in TEST_()
1510 COMPARE(fcvtas(x2, s3), "fcvtas x2, s3"); in TEST_()
1511 COMPARE(fcvtas(w4, d5), "fcvtas w4, d5"); in TEST_()
1512 COMPARE(fcvtas(x6, d7), "fcvtas x6, d7"); in TEST_()
/external/llvm/test/MC/Disassembler/AArch64/
Dbasic-a64-instructions.txt1737 # FP16: fcvtas w25, h26
1738 # FP16: fcvtas x27, h28
1791 # CHECK: fcvtas w25, s26
1792 # CHECK: fcvtas x27, s28
1845 # CHECK: fcvtas w25, d26
1846 # CHECK: fcvtas x27, d28
Dneon-instructions.txt2542 # CHECK: fcvtas s12, s13
2543 # CHECK: fcvtas d21, d14
/external/vixl/test/
Dtest-simulator-a64.cc2550 DEFINE_TEST_FP_TO_INT(fcvtas, FPToS, Conversions) in DEFINE_TEST_FP_TO_INT() argument
3953 DEFINE_TEST_NEON_2SAME_FP(fcvtas, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4007 DEFINE_TEST_NEON_2SAME_FP_SCALAR(fcvtas, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
Dtest-disasm-a64.cc2433 COMPARE(fcvtas(w0, s1), "fcvtas w0, s1"); in TEST()
2434 COMPARE(fcvtas(x2, s3), "fcvtas x2, s3"); in TEST()
2435 COMPARE(fcvtas(w4, d5), "fcvtas w4, d5"); in TEST()
2436 COMPARE(fcvtas(x6, d7), "fcvtas x6, d7"); in TEST()
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h604 fcvtas(rd, fn); in Fcvtas()
Dassembler-arm64.h1585 void fcvtas(const Register& rd, const FPRegister& fn);
Dassembler-arm64.cc1985 void Assembler::fcvtas(const Register& rd, const FPRegister& fn) { in fcvtas() function in v8::internal::Assembler
/external/vixl/src/vixl/a64/
Dmacro-assembler-a64.h1225 fcvtas(rd, vn); in Fcvtas()
2260 V(fcvtas, Fcvtas) \
Dassembler-a64.h2192 void fcvtas(const Register& rd, const VRegister& vn);
2198 void fcvtas(const VRegister& vd, const VRegister& vn);
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26692 fcvtas d10, d21 9d5806c4789fdd138c95044b0a6be7e2 da11a50bbdba9b7fee07dfc60c440b9b 0000000000000…
26694 fcvtas s10, s21 dad5e2bfbd10f8c225943927a8ee0f4b cd267c29ff1bd5a3b00d4e7883c11e6a 0000000000000…
26696 fcvtas v10.2d, v21.2d 898cb15a9322d074db2374ffe963dcfa 47ca635f4533a2222a2b8b3d8fbe2a17 7ffffff…
26698 fcvtas v10.4s, v21.4s e53811dc3eef21960db7904ed0a573a9 cf413b5cc0e548f0832d0a5aa16660a4 8000000…
26700 fcvtas v10.2s, v21.2s eed60246be78eb28bd4e8e155db1d357 648c05217134c70db812caceb8bac010 0000000…
26702 fcvtas w21, s10 a568859814bc2f29ebe86d548f89fd05 06abc0ad581d207accdbcb99d5ba495c a568859814bc2…
26704 fcvtas x21, s10 09ee9ad13fbcec9a96862e0a662df0b2 b69d6d0174a35337bc870fbcf765fb87 09ee9ad13fbce…
26706 fcvtas w21, d10 74620b1dc5c35f438b1793371fbbd791 455d2a188c161e8516e24ff7ef7a568c 74620b1dc5c35…
26708 fcvtas x21, d10 3ffb9b004c80449f368a59094cbedd7b 681f7e714f53e5c994a0431232ff0710 3ffb9b004c804…
/external/valgrind/
DNEWS492 340509 arm64: unhandled instruction fcvtas
494 340632 arm64: unhandled instruction fcvtas

12