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Searched refs:getSubReg (Results 1 – 25 of 83) sorted by relevance

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/external/llvm/lib/Target/AMDGPU/
DSIFrameLowering.cpp177 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1); in emitPrologue()
178 unsigned Rsrc23 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2_sub3); in emitPrologue()
180 unsigned Lo = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub0_sub1); in emitPrologue()
181 unsigned Hi = TRI->getSubReg(PreloadedPrivateBufferReg, AMDGPU::sub2_sub3); in emitPrologue()
190 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitPrologue()
191 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitPrologue()
192 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitPrologue()
193 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitPrologue()
DSIFoldOperands.cpp121 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI); in updateOperand()
208 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in foldOperand()
230 if (FoldRC->getSize() == 8 && UseOp.getSubReg()) { in foldOperand()
234 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
237 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand()
272 if (RSUse->getSubReg() != RegSeqDstSubReg) in foldOperand()
340 OpToFold.getSubReg())) in runOnMachineFunction()
DR600ExpandSpecialInstrs.cpp187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
287 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
294 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
302 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
DSIInstrInfo.cpp461 get(Opcode), RI.getSubReg(DestReg, SubIdx)); in copyPhysReg()
463 Builder.addReg(RI.getSubReg(SrcReg, SubIdx)); in copyPhysReg()
803 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
804 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
820 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
823 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
832 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
833 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
839 .addReg(RI.getSubReg(Src0, AMDGPU::sub0)) in expandPostRAPseudo()
840 .addReg(RI.getSubReg(Src1, AMDGPU::sub0)) in expandPostRAPseudo()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DR600ExpandSpecialInstrs.cpp106 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
107 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp466 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
793 SrcSubReg = MOSrc.getSubReg(); in getNextRewritableSource()
797 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
861 return TargetInstrInfo::RegSubRegPair(MODef.getReg(), MODef.getSubReg()); in getNewSource()
917 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
993 SrcSubReg = MOInsertedReg.getSubReg(); in getNextRewritableSource()
999 if (MODef.getSubReg()) in getNextRewritableSource()
1042 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
1050 TrackSubReg = MODef.getSubReg(); in getNextRewritableSource()
1120 if ((SrcSubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
[all …]
DCalcSpillWeights.cpp51 sub = mi->getOperand(0).getSubReg(); in copyHint()
53 hsub = mi->getOperand(1).getSubReg(); in copyHint()
55 sub = mi->getOperand(1).getSubReg(); in copyHint()
57 hsub = mi->getOperand(0).getSubReg(); in copyHint()
DTargetRegisterInfo.cpp225 if (RCI.getSubReg() == Idx) in getMatchingSuperRegClass()
264 unsigned FinalA = composeSubRegIndices(IA.getSubReg(), SubA); in getCommonSuperRegClass()
273 unsigned FinalB = composeSubRegIndices(IB.getSubReg(), SubB); in getCommonSuperRegClass()
283 *BestPreA = IA.getSubReg(); in getCommonSuperRegClass()
284 *BestPreB = IB.getSubReg(); in getCommonSuperRegClass()
DTargetInstrInfo.cpp142 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; in commuteInstructionImpl()
143 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); in commuteInstructionImpl()
144 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg(); in commuteInstructionImpl()
410 if (FoldOp.getSubReg() || LiveOp.getSubReg()) in canFoldCopy()
478 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF); in foldPatchpoint()
839 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric()
1157 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
1181 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1204 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs()
1207 InsertedReg.SubReg = MOInsertedReg.getSubReg(); in getInsertSubregInputs()
DMachineInstr.cpp79 if (SubIdx && getSubReg()) in substVirtReg()
80 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
88 if (getSubReg()) { in substPhysReg()
89 Reg = TRI.getSubReg(Reg, getSubReg()); in substPhysReg()
225 getSubReg() == Other.getSubReg(); in isIdenticalTo()
267 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
316 OS << PrintReg(getReg(), TRI, getSubReg()); in print()
332 if (isUndef() && getSubReg()) in print()
1156 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect()
1217 else if (MO.getSubReg() && !MO.isUndef()) in readsWritesVirtualRegister()
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DOptimizePHIs.cpp111 !SrcMI->getOperand(0).getSubReg() && in IsSingleValuePHICycle()
112 !SrcMI->getOperand(1).getSubReg() && in IsSingleValuePHICycle()
DRegisterCoalescer.cpp273 DstSub = MI->getOperand(0).getSubReg(); in isMoveInstr()
275 SrcSub = MI->getOperand(1).getSubReg(); in isMoveInstr()
278 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in isMoveInstr()
281 SrcSub = MI->getOperand(2).getSubReg(); in isMoveInstr()
328 Dst = TRI.getSubReg(Dst, DstSub); in setRegisters()
422 Dst = TRI.getSubReg(Dst, DstSub); in isCoalescable()
427 return TRI.getSubReg(DstReg, SrcSub) == Dst; in isCoalescable()
765 UseMI->getOperand(0).getSubReg()) in removeCopyByCommutingDef()
864 if (Op.getSubReg() == 0 || Op.isUndef()) in definesFullReg()
909 if (DstOperand.getSubReg() && !DstOperand.isUndef()) in reMaterializeTrivialDef()
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DRegAllocFast.cpp677 if (!MO.getSubReg()) { in setPhysReg()
683 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0); in setPhysReg()
714 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { in handleThroughOperands()
752 } else if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) { in handleThroughOperands()
904 CopyDstSub = MI->getOperand(0).getSubReg(); in AllocateBasicBlock()
905 CopySrcSub = MI->getOperand(1).getSubReg(); in AllocateBasicBlock()
937 if (MO.getSubReg() && MI->readsVirtualRegister(Reg)) in AllocateBasicBlock()
DExpandPostRAPseudos.cpp89 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); in LowerSubregToReg()
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp152 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
156 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
158 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
160 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp250 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
319 if (!Op.getSubReg()) in profit()
323 if (MI->getOperand(1).getSubReg() != 0) in profit()
411 if (Op.getSubReg()) in isProfitable()
574 unsigned SR = Op.getSubReg(); in createHalfInstr()
621 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
624 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
630 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
634 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg()) in splitMemRef()
646 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
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DHexagonAsmPrinter.cpp400 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
401 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
485 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
486 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
497 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
498 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
510 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
511 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
DHexagonInstrInfo.cpp114 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_loreg)) && in isDblRegForSubInst()
115 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::subreg_hireg)); in isDblRegForSubInst()
617 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { in copyPhysReg()
619 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg, in copyPhysReg()
623 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), (RI.getSubReg(DestReg, in copyPhysReg()
625 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg, in copyPhysReg()
660 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), in copyPhysReg()
662 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_loreg), in copyPhysReg()
684 HRI.getSubReg(DestReg, Hexagon::subreg_hireg)). in copyPhysReg()
685 addReg(HRI.getSubReg(SrcReg, Hexagon::subreg_hireg), in copyPhysReg()
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DHexagonSplitConst32AndConst64.cpp139 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg); in runOnMachineFunction()
140 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg); in runOnMachineFunction()
/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.cpp187 unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
188 unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
199 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
200 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
/external/llvm/lib/MC/
DMCRegisterInfo.cpp21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { in getSubReg() function in MCRegisterInfo
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp357 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
358 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
359 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
360 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
362 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
363 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
364 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
365 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
368 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
369 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp203 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg(); in processBlock()
204 unsigned KilledProdSubReg = MI->getOperand(KilledProdOp).getSubReg(); in processBlock()
205 unsigned OtherProdSubReg = MI->getOperand(OtherProdOp).getSubReg(); in processBlock()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp552 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi()
553 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi()
577 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
580 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
596 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in expandExtractElementF64()
657 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) in expandBuildPairF64()
678 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) in expandBuildPairF64()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h789 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
804 getOperand(0).getSubReg() == getOperand(1).getSubReg();

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