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Searched refs:regList (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/Target/WebAssembly/
DWebAssemblyRegisterInfo.td20 class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>
21 : RegisterClass<"WebAssembly", regTypes, alignment, regList>;
/external/llvm/include/llvm/Target/
DTargetCallingConv.td79 class CCAssignToReg<list<Register> regList> : CCAction {
80 list<Register> RegList = regList;
85 class CCAssignToRegWithShadow<list<Register> regList,
87 list<Register> RegList = regList;
DTarget.td152 dag regList, RegAltNameIndex idx = NoRegAltName>
183 dag MemberList = regList;
/external/llvm/lib/Target/NVPTX/
DNVPTXRegisterInfo.td18 class NVPTXRegClass<list<ValueType> regTypes, int alignment, dag regList>
19 : RegisterClass <"NVPTX", regTypes, alignment, regList>;
/external/llvm/test/TableGen/
Dcast.td41 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
43 list<Register> MemberList = regList;
DTargetInstrSpec.td42 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
44 list<Register> MemberList = regList;
DSlice.td35 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
37 list<Register> MemberList = regList;
DMultiPat.td45 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
47 list<Register> MemberList = regList;
/external/dexmaker/src/dx/java/com/android/dx/ssa/back/
DFirstFitLocalCombiningAllocator.java656 ArrayList<RegisterSpec> regList in analyzeInstructions()
659 if (regList == null) { in analyzeInstructions()
660 regList = new ArrayList<RegisterSpec>(); in analyzeInstructions()
661 localVariables.put(local, regList); in analyzeInstructions()
664 regList.add(assignment); in analyzeInstructions()
/external/llvm/lib/Target/SystemZ/
DSystemZRegisterInfo.td39 dag regList> {
45 def Bit : RegisterClass<"SystemZ", types, size, regList> {
/external/valgrind/VEX/priv/
Dguest_arm_toIR.c12593 UInt regList ) in mk_ldm_stm() argument
12632 if ((regList & (1 << i)) != 0) in mk_ldm_stm()
12651 if (0 == (regList & (1<<r))) in mk_ldm_stm()
12672 if (bW == 0 && (regList & (1<<rN)) != 0) { in mk_ldm_stm()
15518 UInt regList = insn & 0xFFFF; in disInstr_ARM_WRK() local
15527 if (regList == 0) goto after_load_store_multiple; in disInstr_ARM_WRK()
15532 if (bW == 1 && bL == 1 && ((1 << rN) & regList) > 0) in disInstr_ARM_WRK()
15544 mk_ldm_stm( True/*arm*/, rN, bINC, bBEFORE, bW, bL, regList ); in disInstr_ARM_WRK()
15549 rN, bW ? "!" : "", regList); in disInstr_ARM_WRK()
18512 UInt regList = INSN0(7,0); in disInstr_THUMB_WRK() local
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/external/llvm/docs/
DWritingAnLLVMBackend.rst486 list<ValueType> regTypes, int alignment, dag regList> {
496 dag MemberList = regList;
523 * The final argument, ``regList``, specifies which registers are in this class.
524 If an alternative allocation order method is not specified, then ``regList``